Datasheet > PPXN2010VLQ120R

PPXN2010VLQ120R

更新时间： 2024-02-28 03:40:33

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
30页	137K
描述
32-bit Power ArchitectureÂ® Microcontrollers for Highly Reliable

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中文翻译

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数据手册

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PPXN2010VLQ120R 数据手册

Features

ADC

BAM

CAN

CMU

CRC

– Analog-to-digital converter

– Boot assist module

– Controller area network controller

– Clock monitoring unit

– Cyclic redundancy check unit

– Cross Triggering Unit

– Error correction code

– Error correction status module

– Enhanced direct memory access controller

– Fault collection and control unit

– Frequency modulated phase locked loop

– Interrupt controller

PMU

PWM

– Power management unit

– Pulse width modulator module

– Redundancy checker

– Real time clock

– Semaphore unit

– System integration unit lite

– Serial peripherals interface controller

– System status and configuration module

– System timer module

– Sine wave generator

– Software watchdog timer

– Temperature sensor

RTC

SEMA4

SIUL

SPI

SSCM

STM

SWG

SWT

TSENS

CTU

ECC

ECSM

eDMA

FCCU

FMPLL

INTC

IRCOSC – Internal RC oscillator

UART/LIN – Universal asynchronous receiver/transmitter/

JTAG

– Joint Test Action Group interface

– Mode entry, clock, reset, & power

local interconnect network

– Wakeup unit

– Crystal oscillator

WKPU

XOSC

PBRIDGE – Peripheral I/O bridge

PIT – Periodic interrupt timer

Figure 2. PXS20 block diagram (continued)

2.3

Operating Parameters

The PXS20 operating parameters are listed as follows:

•

Operating range 0 – 120 MHz

–40 to +105 °C ambient temperature

Fabricated in 90 nm low power process

1.2 V internal logic

Internal voltage regulator (VREG) with integrated ballast transistor

— Single-supply designs offering high integration level to the customer

3.3 V ±10% for digital I/O input supply voltage

Low power design

•

— Dynamic clock gating of core and peripherals

— Software controlled clock gating of peripherals

— Power consumption less than 400 mA

Selectable current slew rate (slow/medium/fast)

3.3 V ± 10% Nexus pin rail. Same as digital I/O rail

Unused pins configurable as GPIO or GPI for unused A/D channel inputs

3.3–5 V ±10% for A/D converter reference and analog input pins

Designed with EMI reduction techniques

— Phase-locked loop (PLL)

•

— System clock with frequency modulation

— On-chip by-pass capacitance

— Software selectable current slew rate control

— Schmitt trigger on selected inputs

•

Configurable pins

PXS20 Product Brief, Rev. 1

Freescale Semiconductor

1...3 4 567 8 9...30

中文翻译

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与PPXN2010VLQ120R相关器件

型号	品牌	获取价格	描述	数据表
PPXN2010VLQ80R	FREESCALE	获取价格	PXS20 Microcontroller
PPXN2010VLT120R	FREESCALE	获取价格	PXD20 Microcontroller
PPXN2010VLT80R	FREESCALE	获取价格	PXD20 Microcontroller
PPXN2010VLU120R	FREESCALE	获取价格	PXD20 Microcontroller
PPXN2010VLU80R	FREESCALE	获取价格	PXD20 Microcontroller
PPXN2010VMM120R	FREESCALE	获取价格	PXS20 Microcontroller
PPXN2010VMM80R	FREESCALE	获取价格	PXS20 Microcontroller
PPXN2010VVU120R	FREESCALE	获取价格	PXD20 Microcontroller
PPXN2010VVU80R	FREESCALE	获取价格	PXD20 Microcontroller
PPXN2020VMG116R	FREESCALE	获取价格	32-bit Power ArchitectureÂ® Dual Core Microco

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