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PM6670 PDF预览

PM6670

更新时间: 2024-02-10 12:21:30
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 双倍数据速率控制器
页数 文件大小 规格书
53页 684K
描述
Complete DDR2/3 memory power supply controller

PM6670 技术参数

生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN,针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.82
其他特性:ALSO OPERATES WITH 5 VOLT SUPPLY模拟集成电路 - 其他类型:SWITCHING CONTROLLER
控制技术:PULSE WIDTH MODULATION最大输入电压:28 V
最小输入电压:4.5 V标称输入电压:5 V
JESD-30 代码:S-XQCC-N24长度:4 mm
功能数量:1端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
最大输出电流:1.4 A封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE认证状态:Not Qualified
座面最大高度:0.8 mm表面贴装:YES
切换器配置:PUSH-PULL温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD宽度:4 mm
Base Number Matches:1

PM6670 数据手册

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PM6670  
Complete DDR2/3 memory power supply controller  
Preliminary Data  
Features switching  
Switching section (VDDQ)  
– 4.5V to 28V input voltage range  
– 0.9V, 1 voltage reference  
– 1.8V (DDR2) or 1.5V (DDR3) fixed output  
voltages  
– 0.9V to 2.6V adjustable output voltage  
– 1.237V 1ꢀ reference voltage available  
VFQFPN-24 4x4  
– Very fast load transient response using  
constant on-time control loop  
Description  
– No R  
current sensing using low side  
SENSE  
The device PM6670 is a complete DDR2/3 power  
supply regulator designed to meet JEDEC  
specifications.  
MOSFET’s R  
DS(ON)  
– Negative current limit  
– Latched OVP and UVP  
It integrates a Constant On-Time (C.O.T.) buck  
controller, a 2Apk sink/source Low Drop Out  
regulator and a 15mA low noise buffered  
reference.  
– Soft start internally fixed at 3ms  
– Selectable pulse skipping at light load  
– Selectable No-Audible (33KHz) pulse skip  
mode  
The C.O.T. architecture assures fast transient  
response supporting both electrolytic and ceramic  
output capacitors. An embedded integrator  
control loop compensates the DC voltage error  
due to the output ripple.  
– Ceramic output capacitors supported  
– Output voltage ripple compensation  
VTT LDO and VTTREF  
– 2Apk LDO with foldback for VTT  
– Remote VTT sensing  
The 2Apk sink/source linear regulator provides  
the memory termination voltage with fast load  
transient response.  
– High-Z VTT output in S3  
– Ceramic output capacitors supported  
15mA Low noise buffered reference  
The device is fully compliant with system sleep  
states S3 and S4/S5, providing LDO output high  
impedance in Suspend-To-RAM and Tracking  
Discharge of all outputs in Suspend-To-Disk.  
Applications  
DDR2/3 memory supply  
Notebook computers  
Handheld and PDAs  
CPU and chipset I/O supplies  
SSTL18, SSTL15 and HSTL bus termination  
Table 1. Device summary  
Part number  
Package  
VFQFPN-24 4x4 (Exposed Pad)  
Packaging  
PM6670  
Tube  
March 2007  
Rev 1  
1/53  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
53  

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