Datasheet > PL602-37OC-R

PL602-37OC-R

更新时间： 2024-01-05 07:14:35

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
10页	467K
描述
IC CLK BUFFER 800MHZ 16TSSOP

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数据手册

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PL602-37OC-R 数据手册

PL602-35/-37/-38/-39

750kHz – 800MHz Low Phase Noise Multiplier XO

Universal Low Phase Noise IC’s

FEATURES

PIN CONFIGURATION

(Top View)



Selectable 750kHz to 800MHz range.

Low phase noise output

VDD

XIN

SEL0^

SEL1^

GND



-127dBc/Hz for 155.52MHz @ 10kHz offset

-115dBc/Hz for 622.08MHz @ 10kHz offset



LVCMOS (PL602-37), LVPECL (PL602-35 and

PL602-38) or LVDS (PL602-39) output.

12MHz to 25MHz crystal input.

No external crystal load capacitors required.

Output Enable selector.

Selectable /16 to x32 frequency divider/multiplier.

3.3V operation.

Available in 16-Pin TSSOP or 16-pin 3x3mm QFN

GREEN/RoHS compliant packages.

XOUT

SEL3^

SEL2^

CLKC

VDD



CLKT

GND

TSSOP-16L

DESCRIPTION

The PL602-35 (LVPECL with inverted OE), PL602-37

(LVCMOS), PL602-38 (LVPECL), and PL602-39

(LVDS) are high performance and low phase noise XO

IC chips. They provide phase noise performance as

low as –127dBc at 10kHz offset (at 155MHz), by multi-

plying the input crystal frequency up to 32x. The very

low jitter makes them ideal for a wide range of applica-

tions, including SONET/SDH and FEC. They accept

fundamental parallel resonant mode crystals from

12MHz to 25MHz.

XOUT

GND

CLKC

VDD

SEL3^

SEL2^

PL602-3x

CLKT

BLOCK DIAGRAM

QFN-16L

^: Internal pull-up

SEL[3:0]

*: On QFN package, PL602-35/-38 do not have SEL0 available: Pin 10

is VDD, pin 11 is GND. However, PL602-37/-39 have SEL0 (pin 10),

and pin11 is VDD. See pin assignment table for details.

Note: On QFN package there is a large center pad for thermal relief.

This pad needs to be connected to GND.

PLL

CLKC

Oscillator

Amplifier

integrated

load cap.

(Phase

Locked

Loop)

CLKT

OUTPUT ENABLE LOGICAL LEVELS

XIN

Part #

State

XOUT

0 (Default) Output enabled

PLL by-pass

PL602-38

Tri-state

PL602-3x

PL602-35

PL602-37

PL602-39

1 (Default) Output enabled

OE input: Logical states defined by LVPECL levels for PL602-38

Logical states defined by LVCMOS levels for PL602-37/-39

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 03/07/2012 Page 1

12 3 4 5 6 7...10

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PL602-38QC-R	MICROCHIP	获取价格	IC CLK BUFFER
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