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PCS809NRIURFT PDF预览

PCS809NRIURFT

更新时间： 2024-01-18 13:56:51
品牌 Logo 应用领域
PULSECORE 微处理器监控
页数 文件大小 规格书
8页 516K
描述
Power Supply Support Circuit, Fixed, 1 Channel, PDSO3, ROHS COMPLIANT, SOT-23, 3 PIN

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PCS809NRIURFT 技术参数

生命周期：Obsolete包装说明：ROHS COMPLIANT, SOT-23, 3 PIN
Reach Compliance Code：unknown风险等级：5.84
其他特性：POWER-ON RESET GENERATOR; RESET THRESHOLD VOLTAGE IS 3.1V可调阈值：NO
模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUITJESD-30 代码：R-PDSO-G3
长度：2.9 mm信道数量：1
功能数量：1端子数量：3
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.45 mm
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：0.9 V
标称供电电压 (Vsup)：3.2 V表面贴装：YES
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.95 mm端子位置：DUAL
宽度：1.6 mmBase Number Matches：1

PCS809NRIURFT 数据手册

 浏览型号PCS809NRIURFT的Datasheet PDF文件第1页浏览型号PCS809NRIURFT的Datasheet PDF文件第2页浏览型号PCS809NRIURFT的Datasheet PDF文件第4页浏览型号PCS809NRIURFT的Datasheet PDF文件第5页浏览型号PCS809NRIURFT的Datasheet PDF文件第6页浏览型号PCS809NRIURFT的Datasheet PDF文件第7页 
January 2007  
rev 0.2  
PCS809/PCS810  
Detailed Description  
RESET OUTPUT  
returns above the reset threshold, and RESET remains  
low for the reset timeout period.  
µP will be activated at a valid reset state. These µP  
supervisory circuits assert reset to prevent code execution  
errors during power-up, power-down, or brownout  
conditions.  
BENEFITS  
OF  
HIGHLY  
ACCURATE  
RESET  
THRESHOLD  
RESET is guaranteed to be  
a
logic low for  
PCS809/810 with specified voltage as 5V±10% or  
3V±10% are ideal for systems using a 5V±5% or 3V±5%  
power supply. The reset is guaranteed to assert after the  
power supply falls out of regulation, but before power  
drops below the minimum specified operating voltage  
range of the system ICs. The pre-trimmed thresholds are  
reducing the range over which an undesirable reset may  
occur.  
VTH>VCC>0.9V. Once VCC exceeds the reset threshold,  
an internal timer keeps RESET low for the reset timeout  
period; after this interval, RESET goes high.  
If a brownout condition occurs (VCC drops below the reset  
threshold), RESET goes low. Any time VCC goes below  
the reset threshold, the internal timer resets to zero, and  
RESET goes low. The internal timer is activated after VCC  
Application Information  
NEGATIVE-GOING VCC TRANSIENTS  
VCC below 0.9V. However in applications where RESET  
must be valid down to 0V, adding a pull-down resistor to  
RESET causes any leakage currents to flow to ground,  
holding RESET low.  
In addition to issuing a reset to the µP during power-up,  
power-down, and brownout conditions, PCS809 series are  
relatively resistant to short-duration negative-going VCC  
transient.  
ENSURING  
VCC=0  
A
VALID RESET OUTPUT DOWN TO  
INTERFACING TO µP WITH BIDIRECTIONAL RESET  
PINS  
When VCC falls below 0.9V, PCS809 RESET output no  
longer sinks current; it becomes an open circuit. In this  
case, high-impedance CMOS logic inputs connecting to  
RESET can drift to undetermined voltages. Therefore,  
PCS809/810 with CMOS is perfect for most applications of  
The RESET output on the PCS809 is open drain, this  
device interfaces easily with µPs that have bidirectional  
reset pins. Connecting the µP supervisor’s RESET output  
directly to the microcontroller’s RESET pin with a single  
pull-up resistor allows either device to assert reset.  
3-Pin µP Voltage Supervisor  
3 of 8  
Notice: The information in this document is subject to change without notice.  
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