Offset, Gain, And Temperature Drift
sixteen times (16x oversampling) the standard audio word
bit length of 24 bits (44.1kHz x 16 x 24 = 16.9MHz). Note
that this clock rate accommodates a 24-bit word length, even
though only 20 bits are actually being used. The maximum
clock rate of 25MHz is guaranteed, but is not 100% final
tested. The setup and hold timing relationships are shown in
Figure 3.
Although the PCM63P is primarily meant for use in dy-
namic applications, specifications are also given for more
traditional DC parameters such as gain error, bipolar zero
offset error, and temperature gain and offset drift.
DIGITAL INPUT
“Stopped Clock” Operation
Timing Considerations
The PCM63P is normally operated with a continuous clock
input signal. If the clock is to be stopped between input data
words, the last 20 bits shifted in are not actually shifted from
the serial register to the latched parallel DAC register until
Latch Enable (LE, P20) goes low. Latch Enable must remain
low until after the first clock cycle of the next data word
to insure proper DAC operation. In any case, the setup and
hold times for Data and LE must be observed as shown in
Figure 3.
The PCM63P accepts TTL compatible logic input levels.
Noise immunity is enhanced by the use of differential
current mode logic input architectures on all input signal
lines. The data format of the PCM63P is binary two’s
complement (BTC) with the most significant bit (MSB)
being first in the serial input bit stream. Table II describes
the exact relationship of input data to voltage output coding.
Any number of bits can precede the 20 bits to be loaded,
since only the last 20 will be transferred to the parallel DAC
register after LE (P20, Latch Enable) has gone low.
>20ns
All DAC serial input data (P21, DATA) bit transfers are
triggered on positive clock (P18, CLK) edges. The serial-to-
parallel data transfer to the DAC occurs on the falling edge
of Latch Enable (P20, LE). The change in the output of the
DAC coincides with the falling edge of Latch Enable (P20,
LE). Refer to Figure 2 for graphical relationships of these
signals.
Data
Input
LSB
MSB
>10ns >10ns
Clock
Input
>15ns
>15ns
>1ns
>33ns
Latch
Enable
>10ns
Maximum Clock Rate
>One Clock Cycle
>One Clock Cycle
A typical clock rate of 16.9MHz for the PCM63P is derived
by multiplying the standard audio sample rate of 44.1kHz by
FIGURE 3. Setup and Hold Timing Diagram.
VOLTAGE OUTPUT
DIGITAL INPUT
ANALOG OUTPUT
CURRENT OUTPUT
(With External Op Amp)
1,048,576LSBs
1LSB
7FFFFHEX
00000HEX
FFFFFHEX
80000HEX
Full Scale Range
NA
+Full Scale
Bipolar Zero
Bipolar Zero – 1LSB
–Full Scale
4.00000000mA
3.81469727nA
–1.99999619mA
0.00000000mA
+0.00000381mA
+2.00000000mA
6.00000000V
5.72204590µV
+2.99999428V
0.00000000V
–0.00000572V
–3.00000000V
TABLE II. Digital Input/Output Relationships.
P18 (Clock)
3
4
12 13 14 15 16 17 18 19 20
LSB
1
P21 (Data)
1
2
MSB
P20 (Latch Enable)
P6 (IOUT
)
NOTES: (1) If clock is stopped between input of 20-bit data words, Latch Enable (LE) must remain low until after the first clock cycle of the next 20-bit data
word stream. (2) Data format is binary two’s complement (BTC). Individual data bits are clocked in on the corresponding positive clock edge. (3) Latch Enable
(LE) must remain low at least one clock cycle after going negative. (4) Latch Enable (LE) must be high for at least one clock cycle before going negative.
(5) IOUT changes on negative going edge of Latch Enable (LE).
FIGURE 2. Timing Diagram.
®
7
PCM63P
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