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PCA9536DGKR PDF预览

PCA9536DGKR

更新时间： 2024-02-08 17:25:28
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路光电二极管PC时钟
页数 文件大小 规格书
25页 476K
描述
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS

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中文翻译

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PCA9536DGKR 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA, BGA8,2X4,20针数：8
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.71
JESD-30 代码：R-XBGA-B8JESD-609代码：e1
长度：1.98 mm湿度敏感等级：1
位数：4I/O 线路数量：4
端口数量：1端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：VFBGA
封装等效代码：BGA8,2X4,20封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
电源：2.5/5 V认证状态：Not Qualified
座面最大高度：0.5 mm子类别：Parallel IO Ports
最大供电电压：5.5 V最小供电电压：2.3 V
标称供电电压：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：0.9 mm
uPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches：1

PCA9536DGKR 数据手册

 浏览型号PCA9536DGKR的Datasheet PDF文件第6页浏览型号PCA9536DGKR的Datasheet PDF文件第7页浏览型号PCA9536DGKR的Datasheet PDF文件第8页浏览型号PCA9536DGKR的Datasheet PDF文件第10页浏览型号PCA9536DGKR的Datasheet PDF文件第11页浏览型号PCA9536DGKR的Datasheet PDF文件第12页 
PCA9536  
REMOTE 4-BIT I2C AND SMBus I/O EXPANDER  
WITH CONFIGURATION REGISTERS  
www.ti.com  
SCPS125C–APRIL 2006–REVISED NOVEMBER 2006  
Reads  
The bus master first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 4 for device  
address). The command byte is sent after the address and determines which register is accessed. After a  
restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined  
by the command byte then is sent by the PCA9536 (see Figure 8 and Figure 9). After a restart, the value of the  
register defined by the command byte matches the register being accessed when the restart occurred. Data is  
clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data  
bytes received in one read transmission, but when the final byte is received, the bus master must not  
acknowledge the data.  
ACK From  
Master  
ACK From  
Slave  
ACK From  
Slave  
ACK From  
Slave  
Data from Register  
Data  
Slave Address  
Slave Address  
Command Byte  
A
S
A
1
0
0
0
0
0
1
1
A
S
1
0
0
0
0
0
1
0
A
R/W  
At this time, the master-transmitter  
becomes master-receiver and  
slave-receiver becomes  
R/W  
slave-transmitter  
Data from Register  
NACK From Master  
Data  
P
NA  
Last Byte  
Figure 8. Read From Register  
<br/>  
1
2
3
4
5
6
7
8
9
SCL  
SDA  
Data From Port  
Data 1  
Slave Address  
Data From Port  
Data 4  
S
1
0
0
0
0
0
1
0
A
P
NA  
A
Start  
Condition  
NACK From  
Master  
ACK From  
Slave  
ACK From  
Master  
Stop  
Condition  
R/W  
Read From  
Port  
Data Into  
Port  
Data 2  
Data 3  
Data 4  
Data 5  
t
ph  
t
ps  
A. This figure assumes that the command byte previously has been programmed with 00h.  
B. Transfer of data can be stopped at any moment by a Stop condition.  
C. This figure eliminates the command byte transfer, a restart, and the slave address call between the initial slave  
address call and actual data transfer from the P-port (see Figure 8).  
Figure 9. Read Input Port Register  
9
Submit Documentation Feedback  
 
 
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中文翻译

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PCA9536DGKR 替代型号

型号 品牌 替代类型 描述 数据表
PCA9536DR TI

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 REMOTE 4-BIT I2C AND SMBus I/O EXPANDER WITH CONFIGURATION REGISTERS

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