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PCA9534DBR PDF预览

PCA9534DBR

更新时间: 2024-02-13 20:36:01
品牌 Logo 应用领域
德州仪器 - TI 并行IO端口微控制器和处理器外围集成电路光电二极管输出元件时钟
页数 文件大小 规格书
32页 658K
描述
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS

PCA9534DBR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.82Is Samacsys:N
最大时钟频率:0.4 MHzJESD-30 代码:S-PQCC-N16
JESD-609代码:e4长度:4 mm
湿度敏感等级:2位数:8
I/O 线路数量:8端口数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC16,.16SQ,25
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260电源:2.5/5 V
认证状态:Not Qualified座面最大高度:1 mm
子类别:Parallel IO Ports最大压摆率:0.175 mA
最大供电电压:5.5 V最小供电电压:2.3 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
uPs/uCs/外围集成电路类型:PARALLEL IO PORT, GENERAL PURPOSEBase Number Matches:1

PCA9534DBR 数据手册

 浏览型号PCA9534DBR的Datasheet PDF文件第1页浏览型号PCA9534DBR的Datasheet PDF文件第2页浏览型号PCA9534DBR的Datasheet PDF文件第4页浏览型号PCA9534DBR的Datasheet PDF文件第5页浏览型号PCA9534DBR的Datasheet PDF文件第6页浏览型号PCA9534DBR的Datasheet PDF文件第7页 
PCA9534  
REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER  
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS  
www.ti.com  
SCPS124BSEPTEMBER 2006REVISED FEBRUARY 2007  
TERMINAL FUNCTIONS  
NO.  
QSOP (DBQ),  
SOIC (DW),  
SSOP (DB),  
QFN (RGT)  
AND  
NAME  
DESCRIPTION  
TSSOP (PW), AND  
TVSOP (DGV)  
QFN (RGV)  
1
2
15  
16  
1
A0  
A1  
Address input. Connect directly to VCC or ground.  
Address input. Connect directly to VCC or ground.  
Address input. Connect directly to VCC or ground.  
P-port input/output. Push-pull design structure.  
P-port input/output. Push-pull design structure.  
P-port input/output. Push-pull design structure.  
P-port input/output. Push-pull design structure.  
Ground  
3
A2  
4
2
P0  
5
3
P1  
6
4
P2  
7
5
P3  
8
6
GND  
P4  
9
7
P-port input/output. Push-pull design structure.  
P-port input/output. Push-pull design structure.  
P-port input/output. Push-pull design structure.  
P-port input/output. Push-pull design structure.  
Interrupt output. Connect to VCC through a pullup resistor.  
Serial clock bus. Connect to VCC through a pullup resistor.  
Serial data bus. Connect to VCC through a pullup resistor.  
Supply voltage  
10  
11  
12  
13  
14  
15  
16  
8
P5  
9
P6  
10  
11  
12  
13  
14  
P7  
INT  
SCL  
SDA  
VCC  
LOGIC DIAGRAM (POSITIVE LOGIC)  
13  
Interrupt  
Logic  
LP Filter  
INT  
1
A0  
2
A1  
P7−P0  
3
A2  
14  
SCL  
2
Input  
Filter  
I C Bus  
Control  
Shift  
Register  
I/O  
Port  
15  
8 Bits  
SDA  
Write Pulse  
Read Pulse  
Power-On  
Reset  
16  
V
CC  
8
GND  
A. Pin numbers shown are for DB, DBQ, DGV, DW, or PW package.  
B. All I/Os are set to inputs at reset.  
3
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