Datasheet > P0060SB

P0060SB

更新时间： 2022-02-26 13:01:53

品牌	Logo	应用领域
雷卯电子 - LEIDITECH		/
页数	文件大小	规格书
9页	567K
描述
Thyristor Surge Suppressors

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P0060SB 数据手册

Thyristor Surge Suppressors

P0060~P3500SA_B_C Series

Soldering Parameters

Figure 5. Test circuit 3 for dynamic I parameter

Pb-Free assembly

Figure 1

(see Fig. 1)

t_P

Surge generator

T_P

-Temperature Min (T

-Temperature Max (T

-Time (Min to Max) (t

)

s(min)

Critical Zone

T_LtoT_P

Ramp-up

)

Pre Heat

s(max)

)

60-180 secs.

T_L

t_L

Average ramp up rate (LiquidusTemp (T

=- 48 V

)

D.U.T

T_S(max)

BAT

3°C/sec. Max.

to peak)

Ramp-down

T_S(max)to T_L- Ramp-up Rate

3°C/sec. Max.

Preheat

-Temperature (T _L) (Liquidus)

-Temperature (t

T_S(min)

t_S

)

60-150 secs.

Peak Temp (T_P)

Time within 5°C of actual PeakTemp (t )

time to peak temperature

30 secs. Max.

Time

This is a GO-NOGO test which allows to confirm the holding current (I ) level in a^{(t 25ºC to peak)}

Ramp-down Rate

functional test circuit.

6°C/sec. Max.

Time 25°C to PeakTemp (T_P)

8 min. Max.

Do not exceed

TEST PROCEDURE

1/ Adjust the current level at the Iv alue by short circuiting the AK of the D.U.T.

2/ Fire the D.U.T.w ith a surge current

PP 10A, 10/1000µs.

3/ The D.U.T.w ill come back off-state within 50ms maximum.

80% Rated V_DRM(V_ACPeak

High TempVoltage

Blocking

Lead Material

Copper Alloy

504 or 1008 hrs. MIL- STD-750 (Method 1040)

JEDEC, JESD22-A-101

Terminal Finish

100% Matte-Tin Plated

Temp Cycling

cycles. MIL- STD-750 (Method 1051) EIA/JEDEC,

JESD22-A104

Body Material

52 V

Biased Temp &

Humidity

JEDEC, JESD22-A-101

High Temp Storage

LowTemp Storage

JEDEC, JESD22-A-101

-65°C, 1008 hrs.

Thermal Shock

10 cycles. MIL- STD-750 (Method 1056) JEDEC,

JESD22-A-106

Autoclave (Pressure

Cooker Test)

JEDEC, JESD22-A-102

Resistance to Solder

Heat

Moisture Sensitivity

Level

1...4 5 678 9

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