OP191/OP291/OP491
(@ V = +3.0 V, V = 0.1 V, T = +25°C unless otherwise noted)
WAFER TEST LIMITS
P aram eter
S
CM
A
Sym bol
Conditions
Lim it
Units
Offset Voltage
Input Bias Current
Input Offset Current
VOS
IB
IOS
±300
50
8
µV max
nA max
nA
Input Voltage Range
VCM
CMRR
PSRR
AVO
VOH
VOL
ISY
V– to V+
70
80
50
2.8
V min
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Large Signal Voltage Gain
Output Voltage High
Output Voltage Low
VCM = 0 V to +2.9 V
V = 2.7 V to +12 V
RL = 10 kΩ
RL = 2 kΩ to GND
RL = 2 kΩ to V+
VO = 0 V, RL = ∞
dB min
dB min
V/mV min
V min
mV max
µA max
75
350
Supply Current/Amplifier
NOT E
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +16 V
Tem perature
Range
P ackage
D escription
P ackage
O ption
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . GND to VS + 10 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage T emperature Range
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating T emperature Range
OP191/OP291/OP491G . . . . . . . . . . . . . . . –40°C to +125°C
Junction T emperature Range
P, S, RU Packages . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature Range (Soldering 60 sec) . . . . . . . . +300°C
Model
OP191GP
OP191GS
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
DICE
–40°C to +125°C 8-Pin Plastic DIP N-8
–40°C to +125°C 8-Pin SOIC SO-8
DICE
–40°C to +125°C 14-Pin Plastic DIP N-14
OP191GBC +25°C
OP291GP
OP291GS
OP291GBC +25°C
OP491GP
OP491GS
–40°C to +125°C 14-Pin SOIC
SO-14
RU-14
OP491HRU –40°C to +125°C 14-Pin T SSOP
OP491GBC +25°C DICE
2
P ackage Type
θJA
θJC
Units
8-Pin Plastic DIP (P)
8-Pin SOIC (S)
14-Pin Plastic DIP (P)
14-Pin SOIC (S)
103
158
76
120
180
43
43
33
36
35
°C/W
°C/W
°C/W
°C/W
°C/W
14-Pin T SSOP (RU)
NOT ES
1Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2θJA is specified for the worst case conditions; i.e., θJA is specified for device in socket
for P-DIP packages; θJA is specified for device soldered in circuit board for T SSOP
and SOIC packages.
2
14
13
1
D ICE CH ARACTERISTICS
12
11
10
3
4
5
1
7
8
7
2
3
2
3
6
5
6
4
4
9
7
8
6
OP191 Die Size 0.047 × 0.066 Inch,
3,102 Sq. Mils. Substrate (Die Back-
side) Is Connected to V+.
OP291 Die Size 0.070 × 0.070 Inch,
4,900 Sq. Mils. Substrate (Die Back-
side) Is Connected to V+.
OP491 Die Size 0.070 × 0.110 Inch,
7,700 Sq. Mils. Substrate (Die Back-
side) Is Connected to V+.
Transistor Count, 74.
Transistor Count, 146
Transistor Count, 290.
REV. 0
–5–
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