Datasheet > NM9820

NM9820

更新时间： 2022-12-22 05:38:51

品牌	Logo	应用领域
其他 - ETC		PC
页数	文件大小	规格书
18页	121K
描述
Single PCI UART

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数据手册

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NM9820 数据手册

Nm9820

NetMos

Technology

Single PCI UART

Pin Name

128

Type

Description

CLK

122

121

33 MHz PCI system clock input.

nRESET

PCI System reset (avtice low). Resets all internal register, sequencers, and

signals to a consistent state. During reset condition AD31-0, nSER are three-

stated.

AD31-29 126-128

I/O

Multiplexed PCI address / data bus. A bus transaction consists of an address

phase followed by one or more data phase. During the address phase AD31-

0 contain a physical address. Write data is stable and valid when nIRDY and

nTRDY are asserted (active).

AD28-24

2-6

I/O

See AD31-29 description.

AD23-16 11-18

AD15-11 34-38

AD10-8

AD7-0

40-42

46-53

nFRAME

Frame is driven by the current master to indicate the beginning and duration

of an access. nFRAME is asserted to indicate a bus transaction is beginning.

While nFRAME is active, data transfer continues.

nIRDY

Initiator Ready. During a write, nIRDY asserted indicates that the initiator is

driving valid data onto the data bus. During a read, nIRDY asserted indicates

that the initiator is ready to accept data from the Nm9820.

nTRDY

nSTOP

nLOCK

IDSEL

Target Ready (three-state). It is asserted when Nm9820 is ready to complete

the current data phase.

Nm9820 asserts nSTOP to indicate that it wishes the initiator to stop the

transaction in process on the current data phase.

Lock indicates an atomic operation that my require multiple transactions to

complete.

Initialization Device Select. It is used as a chip select during configuration

read and writes transactions.

nDEVSEL 26

Device Select (three-state). Nm9820 asserts nDEVSEL when the Nm9820

has decoded its address.

Page 1-35

Rev. 1.0

1 234 5 6 7...18

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