Datasheet > NM9805CV

NM9805CV

更新时间： 2022-11-24 21:50:58

品牌	Logo	应用领域
其他 - ETC		PC
页数	文件大小	规格书
16页	94K
描述
PCI + 1284 Printer Port

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数据手册

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NM9805CV 数据手册

Nm9805

PCI + 1284 Printer Port

Pin Name

128

Type

Description

actions except a special cycle. The minimum duration of nPERR is one clock

cycle.

nSERR

PAR

System Error (open drain). This pin goes low when address parity errors are

detected.

I/O

Even Parity. Parity is even parity acrossAD31-0 and nC/BE3-0. PAR is stable

and valid one clock after the address phase. For data phase, PAR is stable

and valid one clock after either nIRDY is asserted on a write transaction, or

nTRDY is asserted on a read transaction.

nC/BE3

nC/BE2

nC/BE1

nC/BE0

Bus Command and Byte Enable. During the address phase of a transaction,

nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used

as byte enables. nC/BE3 applies to byte “3”.

Bus Command and Byte Enable. During the address phase of a transaction,

nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used

as byte enables. nC/BE2 applies to byte “2”.

Bus Command and Byte Enable. During the address phase of a transaction,

nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used

as byte enables. nC/BE1 applies to byte “1”.

Bus Command and Byte Enable. During the address phase of a transaction,

nC/BE3-0 defines the bus command. During data phase, nC/BE3-0 are used

as byte enables. nC/BE0 applies to byte “0”.

nINTA

120

115

PCI active low interrupt output (open-drain). This signal goes low (active)

when an interrupt condition occurs.

EE-CS

External EEprom chip select (active high). After power on reset, Nm9805

reads the EE-Prom and loads the read-only configuration registers sequen-

tially from the first 64 bytes in the EE-Prom.

EE-CLK

EE-DI

116

118

117

123

External EEprom clock.

External EEprom data input.

External EEprom data output.

EE-DO

EE-EN

Enable/Disable external EEprom (active high, internal pull-up). External

EEprom can be disabled when this pin is tied to GND or pulled low. When

external EEprom is disabled, the default values for Nm9805 will be loaded

into PCI configuration register.

Page 5

Rev. 1.1

1 2 3 456 7 8...16

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