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NLX2G08DMUTWG PDF预览

NLX2G08DMUTWG

更新时间: 2024-02-25 15:02:26
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路
页数 文件大小 规格书
8页 87K
描述
Dual 2-Input AND Gate

NLX2G08DMUTWG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:End Of Life包装说明:VSON,
Reach Compliance Code:compliant风险等级:5.67
系列:NLXJESD-30 代码:R-PDSO-N8
JESD-609代码:e4长度:1.95 mm
逻辑集成电路类型:AND GATE湿度敏感等级:1
功能数量:2输入次数:2
端子数量:8最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):11.2 ns座面最大高度:0.55 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1 mm
Base Number Matches:1

NLX2G08DMUTWG 数据手册

 浏览型号NLX2G08DMUTWG的Datasheet PDF文件第2页浏览型号NLX2G08DMUTWG的Datasheet PDF文件第3页浏览型号NLX2G08DMUTWG的Datasheet PDF文件第4页浏览型号NLX2G08DMUTWG的Datasheet PDF文件第5页浏览型号NLX2G08DMUTWG的Datasheet PDF文件第6页浏览型号NLX2G08DMUTWG的Datasheet PDF文件第7页 
NLX2G08  
Dual 2-Input AND Gate  
The NLX2G08 is an advanced high-speed dual 2-input CMOS  
AND gate in ultra-small footprint.  
The NLX2G08 input structures provide protection when voltages up  
to 7.0 volts are applied, regardless of the supply voltage.  
Features  
www.onsemi.com  
High Speed: t 2.5 ns (typical) at V = 5.0 V  
PD  
CC  
Designed for 1.65 V to 5.5 V V Operation  
CC  
MARKING  
DIAGRAMS  
Low Power Dissipation: I = 1 mA (Max) at T = 25°C  
CC  
A
24 mA Balanced Output Sink and Source Capability  
Balanced Propagation Delays  
Overvoltage Tolerant (OVT) Input Pins  
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS  
Compliant  
1
UQFN8  
MU SUFFIX  
CASE 523AN  
AD MG  
G
8
1
UDFN8  
1.45 x 1.0  
X M  
CASE 517BZ  
1
A1  
B1  
1
2
3
4
8
7
6
5
V
CC  
A1  
7
B1  
6
Y2  
5
UDFN8  
1.6 x 1.0  
CASE 517BY  
X M  
X M  
1
Y1  
B2  
A2  
V
CC  
GND  
4
UDFN8  
1.95 x 1.0  
CASE 517CA  
8
1
Y2  
XX  
M
G
= Specific Device Code  
= Date Code  
= Pb−Free Package  
1
Y1  
2
B2  
3
A2  
GND  
(Note: Microdot may be in either location)  
Figure 1. Pinouts  
IEEE/IEC  
&
A1  
B1  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
Y1  
Y2  
A2  
B2  
PIN ASSIGNMENT  
Figure 2. Logic Symbol  
Pin  
Function  
(UQFN8)  
Function  
(ULLGA/  
UDFN)  
FUNCTION TABLE  
Y = AB  
1
2
3
4
5
6
7
8
Y1  
B2  
A1  
B1  
Inputs  
Output  
A
L
B
L
Y
L
A2  
Y2  
GND  
Y2  
GND  
A2  
L
H
L
L
H
H
L
B1  
B2  
H
H
A1  
Y1  
H = HIGH Logic Level  
L = LOW Logic Level  
V
CC  
V
CC  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
June, 2018 − Rev. 9  
NLX2G08/D  

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