Datasheet > NJG1516R-TE1

NJG1516R-TE1

更新时间： 2024-01-07 01:14:36

品牌	Logo	应用领域
NJRC		/
页数	文件大小	规格书
14页	289K
描述
RF/Microwave Switch

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技术参数
数据手册

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NJG1516R-TE1 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.81
JESD-609代码：	e6	端子面层：	Tin/Bismuth (Sn/Bi)
Base Number Matches：	1

NJG1516R-TE1 数据手册

NJG1516R

QTERMINAL INFORMATION

No.

SYMBOL

VCTL2

EXPLANATION

Control port 2. The voltage of this port controls PC to P2 state. The ‘ON’

and ‘OFF’ state is toggled by controlling voltage of this terminal such as

high-state (2.7~5.5V) or low-state (-0.2~+0.2V). The voltage of 4^thpin have

to be set to opposite state. The bypass capacitor has to be chosen to

reduce switching speed delay from 10pF~1000pF range.

Common RF port. In order to block the DC bias voltage of internal circuit,

an external capacitor is required. (50~100MHz: 0.01uF, 0.1~0.5GHz:

1000pF, 0.5~2.5GHz: 56pF)

Ground terminal. Please connect this terminal with ground plane as close

as possible for excellent RF performance.

3, 6, 7

GND

Control port 1. The voltage of this port controls PC to P2 state. The ‘ON’

and ‘OFF’ state is toggled by controlling voltage of this terminal such as

high-state (2.7~5.5V) or low-state (-0.2~+0.2V). The voltage of 1^stpin have

to be set to opposite state. The bypass capacitor has to be chosen to

reduce switching speed delay from 10pF~1000pF range.

VCTL1

RF port. This port is connected with PC port by controlling 4^thpin (V_{CTL (H)}

)

to 2.7~9.0V and 1^stpin (V_{CTL (L)}) to -0.2~+0.2V. An external capacitor is

required to block the DC bias voltage of internal circuit. (50~100MHz:

0.01µF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF)

RF port. This port is connected with PC port by controlling 1^stpin (V_{CTL (H)}

)

to 2.7~9.0V and 4^thpin (V_{CTL (L)}) to -0.2~+0.2V. An external capacitor is

required to block the DC bias voltage of internal circuit. (50~100MHz:

0.01µF, 0.1~0.5GHz: 1000pF, 0.5~2.5GHz: 56pF)

- 4-

1 2 345 6 7...14

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