NJ8821
DS3278-1.3
NJ8821
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH RESETTABLE COUNTERS
T
he NJ8821 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-holdcomparators,10-bitprogrammable‘M’counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external control
from a suitable microprocessor..
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
PDA
PDB
LD
CH
RB
MC
DS2
DS1
DS0
PE
F
IN
V
SS
NJ8821
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
V
DD
OSC IN
OSC OUT
D0
The NJ8821 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
NC
D3
range of 230
Ceramic DIL package with operating temperature range of
240 C to 185 C.
°C to 170°C. The NJ8821MA is available only in
DP20, MP20
DG20
D1
D2
°
°
FEATURES
Low Power Consumption
■ Microprocessor Compatible
Fig.1 Pin connections - top view
■
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD2VSS
Input voltage
20·5V to 7V
■
■
High Performance Sample and Hold Phase Detector
>10MHz Input Frequency
7V
Open drain output, pin 3
V
SS20·3V to VDD10·3V
All other pins
ORDERING INFORMATION
Storage temperature
265°C to 1150°C
NJ8821 BA DP Plastic DIL Package
NJ8821 BA MP Miniature Plastic DIL Package
NJ8821 MA DG Ceramic DIL Package
(DG package, NJ8821MA)
255°C to 1125°C
(DP and MP packages, NJ8821)
Storage temperature
DATA SELECT INPUTS
DS0 DS1 DS2
RB
19
CH
20
15 16 17
TO
INTERNAL
LATCHES
14
LATCH SELECT
LOGIC
PROGRAM
ENABLE (PE)
f
REFERENCE COUNTER
(11BITS)
r
7
8
SAMPLE/HOLD
PHASE
DETECTOR
42
OSC IN
1
PDA
OSC OUT
LATCH 6 LATCH 7 LATCH 8
FREQUENCY/
PHASE
DETECTOR
2
3
PDB
9
D0
10
11
12
DATA
INPUTS
D1
D2
D3
LOCK DETECT (LD)
V
SS
LATCH 4 LATCH 5
LATCH 1 LATCH 2 LATCH 3
f
4
v
‘A’ COUNTER
(7 BITS)
‘M’ COUNTER
(10 BITS)
F
IN
6
V
DD
MODULUS
CONTROL
18
CONTROL LOGIC
5
OUTPUT (MC)
V
SS
Fig.2 Block diagram