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NE555T

更新时间: 2024-02-03 17:12:05
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
7页 124K
描述
IC PULSE; RECTANGULAR, TIMER, MBCY8, Analog Waveform Generation Function

NE555T 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:DIE包装说明:DIE,
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.65
其他特性:CAN ALSO OPERATE FROM A 15V NOMINAL SUPPLY模拟集成电路 - 其他类型:PULSE; RECTANGULAR
JESD-30 代码:X-XUUC-N功能数量:1
最高工作温度:70 °C最低工作温度:
封装主体材料:UNSPECIFIED封装代码:DIE
封装形状:UNSPECIFIED封装形式:UNCASED CHIP
认证状态:Not Qualified最大供电电压 (Vsup):16 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:NO LEAD端子位置:UPPER
Base Number Matches:1

NE555T 数据手册

 浏览型号NE555T的Datasheet PDF文件第1页浏览型号NE555T的Datasheet PDF文件第2页浏览型号NE555T的Datasheet PDF文件第3页浏览型号NE555T的Datasheet PDF文件第4页浏览型号NE555T的Datasheet PDF文件第5页浏览型号NE555T的Datasheet PDF文件第6页 
Philips Semiconductors Linear Products  
Product specification  
Timer  
NE/SA/SE555/SE555C  
TYPICAL APPLICATIONS  
V
CC  
V
V
CC  
CC  
10k  
1/3 V  
O
CC  
.001µF  
2
555  
VOLTS  
1
DURATION OF  
TRIGGER PULSE AS  
SEEN BY THE TIMER  
SWITCH GROUNDED  
AT THIS POINT  
NOTE: All resistor values are in Ω  
Figure 1. AC Coupling of the Trigger Pulse  
Trigger Pulse Width Requirements and Time  
Delays  
Another consideration is the “turn-off time”. This is the measurement  
Due to the nature of the trigger circuitry, the timer will trigger on the  
negative going edge of the input pulse. For the device to time out  
properly, it is necessary that the trigger voltage level be returned to  
some voltage greater than one third of the supply before the time out  
period. This can be achieved by making either the trigger pulse  
sufficiently short or by AC coupling into the trigger. By AC coupling  
the trigger, see Figure 1, a short negative going pulse is achieved  
when the trigger signal goes to ground. AC coupling is most  
frequently used in conjunction with a switch or a signal that goes to  
ground which initiates the timing cycle. Should the trigger be held  
low, without AC coupling, for a longer duration than the timing cycle  
the output will remain in a high state for the duration of the low  
trigger signal, without regard to the threshold comparator state. This  
is due to the predominance of Q on the base of Q , controlling  
of the amount of time required after the threshold reaches 2/3 V  
CC  
to turn the output low. To explain further, Q at the threshold input  
1
turns on after reaching 2/3 V , which then turns on Q , which turns  
CC  
5
on Q . Current from Q turns on Q which turns Q off. This  
6
6
16  
17  
allows current from Q to turn on Q and Q to given an output  
19  
20  
24  
low. These steps cause the 2µs max. delay as stated in the data  
sheet.  
Also, a delay comparable to the turn-off time is the trigger release  
time. When the trigger is low, Q is on and turns on Q which turns  
10  
11  
on Q . Q turns off Q and allows Q to turn on. This turns off  
15  
15  
16  
17  
current to Q and Q , which results in output high. When the  
20  
24  
trigger is released, Q and Q shut off, Q turns off, Q turns on  
10  
11  
15  
16  
and the circuit then follows the same path and time delay explained  
as “turn off time”. This trigger release time is very important in  
designing the trigger pulse width so as not to interfere with the  
output signal as explained previously.  
15  
16  
the state of the bi-stable flip-flop. When the trigger signal then  
returns to a high level, the output will fall immediately. Thus, the  
output signal will follow the trigger signal in this case.  
352  
August 31, 1994  

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