Datasheet > N02L63W2A

N02L63W2A

更新时间： 2022-12-23 07:13:53

品牌	Logo	应用领域
安森美 - ONSEMI		静态存储器
页数	文件大小	规格书
11页	219K
描述
2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K × 16 bit

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N02L63W2A 数据手册

N02L63W2A

Timing Test Conditions

Item

0.1V_CCto 0.9 V_CC

Input Pulse Level

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

5ns

0.5 V_CC

CL = 30pF

-40 to +85 ^oC

Operating Temperature

Timing

2.3 - 3.6 V

2.7 - 3.6 V

Item

Symbol

Units

Min.

Max.

Min.

Max.

t_RC

t_AA

t_CO

t_OE

Read Cycle Time

Address Access Time

Chip Enable to Valid Output

Output Enable to Valid Output

Byte Select to Valid Output

Chip Enable to Low-Z output

Output Enable to Low-Z Output

Byte Select to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Byte Select Disable to High-Z Output

Output Hold from Address Change

Write Cycle Time

_LB, t_UB

t_LZ

t_OLZ

t_LBZ, t_UBZ

t_HZ

t_OHZ

_LBHZ, t_UBHZ

t_OH

t_WC

t_CW

Chip Enable to End of Write

Address Valid to End of Write

Byte Select to End of Write

Write Pulse Width

t_AW

t_LBW, t_UBW

t_WP

t_AS

Address Setup Time

t_WR

Write Recovery Time

t_WHZ

t_DW

Write to High-Z Output

Data to Write Time Overlap

Data Hold from Write Time

End Write to Low-Z Output

t_DH

t_OW

Rev. 9 | Page 6 of 11 | www.onsemi.com

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