Datasheet > MU9C8K64F-50TDI

MU9C8K64F-50TDI

更新时间： 2024-01-23 20:22:16

品牌	Logo	应用领域
MUSIC		双倍数据速率静态存储器内存集成电路
页数	文件大小	规格书
32页	1101K
描述
Content Addressable SRAM, 8KX64, CMOS, PQFP100

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技术参数
数据手册

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MU9C8K64F-50TDI 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
包装说明：	QFP, QFP100,.63X.87	Reach Compliance Code：	unknown
风险等级：	5.8	JESD-30 代码：	R-PQFP-G100
内存密度：	524288 bit	内存集成电路类型：	CONTENT ADDRESSABLE SRAM
内存宽度：	64	湿度敏感等级：	3
端子数量：	100	字数：	8192 words
字数代码：	8000	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	8KX64
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP100,.63X.87	封装形状：	RECTANGULAR
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	最大待机电流：	0.005 A
子类别：	SRAMs	最大压摆率：	0.45 mA
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

MU9C8K64F-50TDI 数据手册

MU9C Routing CoProcessor (RCP) Family

Packet Stream

Controller

Switch Control

And Packet

Data

Switch

Fabric

RCP

Control

Network

Address

Data

RAM

Address

MU9C

RAM

Figure 2: Switch Block Diagram

PIN DESCRIPTIONS

Note: Signal names that start with a slash ("/") are active LOW. All signals are 3.3V CMOS level. Never leave inputs floating. The CAM

architecture draws large currents during compare operations, mandating the use of good layout and bypassing techniques. Refer to the

Electrical Characteristics section for more information.

DQ31-0 (Data Bus, Three-state, Common

Input/ Output)

DSC (Data Segment Control, Input)

When DQ bus access to a 64 bit register or memory word

is performed, the DSC input determines whether bits 31-0

(DSC LOW) or bits 63-32 (DSC HIGH) are accessed.

Access to 32 bit registers require that DSC be held LOW.

The DQ31-0 lines convey data to and from the MU9C

RCP. When the /E input is HIGH the DQ31-0 lines are

held in their high-impedance state. The /W input deter-

mines whether data flows to or from the device on the

DQ31-0 lines. The source or destination of the data is

determined by the AC bus, DSC, and the /AV line. During

a Write cycle, data on the DQ31-0 lines is registered by the

falling edge of /E.

AA12-0/AA11-0 (Active Address, Output)

The AA bus conveys the Match address, the Next Free

address, or Random Access address, depending on the

most recent memory cycle. The /OE input enables the AA

bus; when the /OE input is HIGH, the AA bus is in its

high-impedance state; when /OE is LOW the AA bus is

active. In a vertically cascaded system after a Comparison

cycle, Write at Next Free Address cycle or Read/Write at

Highest-Priority match, only the highest-priority device

will enable its AA bus, regardless of the state of the /OE

input. In the event of a mismatch in the Address Database

after a Compare cycle, or after a Write at Next Free

Address cycle into an already full system, the lowest-pri-

ority device will drive the AA bus with all 1s. The AA bus

is latched when /E is LOW, and are free to change only

when /E is HIGH.

AC12-0/AC11-0 (Address/Control Bus, Input)

When Hardware control is selected, the AC bus conveys

address or control information to the MU9C RCP, depend-

ing on the state of the /AV input. When /AV is LOW then

the AC bus carries an address; when /AV is HIGH the AC

bus carries control information. Data on the AC bus is reg-

istered by the falling edge of /E. When software control is

selected, the state of the AC bus does not affect the opera-

tion of the device.

Rev. 8.10

1 234 5 6 7...32

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