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MU9C3480A-70DI PDF预览

MU9C3480A-70DI

更新时间: 2024-01-04 13:51:39
品牌 Logo 应用领域
MUSIC 局域网
页数 文件大小 规格书
32页 332K
描述
LANCAM A/L series

MU9C3480A-70DI 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
包装说明:QCCJ, LDCC44,.7SQReach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.83最长访问时间:52 ns
其他特性:LANCAMJESD-30 代码:S-PQCC-J44
JESD-609代码:e0内存密度:16384 bit
内存集成电路类型:CONTENT ADDRESSABLE SRAM内存宽度:64
湿度敏感等级:3功能数量:1
端子数量:44字数:256 words
字数代码:256工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:256X64封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC44,.7SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified最大待机电流:0.007 A
子类别:SRAMs最大压摆率:0.055 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

MU9C3480A-70DI 数据手册

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Data Sheet  
LANCAM A/L series (not recommended for new designs)  
APPLICATION BENEFITS  
DISTINCTIVE CHARACTERISTICS  
The 256x64 to 4Kx64 LANCAM A/L series facilitate  
numerous operations:  
High density CMOS Content Addressable Memory  
(CAM)  
Available in the following depths: 256 (3480), 512  
(5480), 1K (1480), 2K (2480) and 4K (4480) words.  
Fast speed allows processing of both DA and SA  
within 450 ns, equivalent to 138 ports of 10 Base-T or  
13 ports of 100 Base-T Ethernet (50 ns device)  
64-bit per word memory organization  
16-bit I/O  
Full CAM features allow all operations to be masked  
on a bit-by-bit basis  
Fast 50 ns compare speed (1480A and 2480A)  
Powerful instruction set for any list processing need  
Dual configuration register set for rapid context  
switching  
Shiftable Comparand and Mask registers assist in  
proximate matching algorithms  
16-bit CAM/RAM segments with MUSIC’s patented  
partitioning  
Cascadable to any practical length with no  
performance penalties  
/MA and /MM output flags to enable faster system  
performance  
Industrial temperature grades for harsh environments  
Available in 3.3 Volt for lower power systems  
Readable Device ID  
Selectable faster operating mode with no wait states  
after a no-match  
Validity bit setting accessible from the Status register  
Single cycle reset for Segment Control register  
5 Volt (A series) or 3.3 Volt (L series) operation  
44-pin PLCC package  
(Use functional compatible LANCAM B family for new designs)  
(also available in Lead-Free package upon request)  
DATA (64)  
MUX  
VCC  
GND  
DATA (16)  
DQ (15—0)  
(16)  
TRANSLATE  
802.3 / 802.5  
DEMUX  
DATA (64)  
DATA (16)  
DATA (16)  
COMPARAND  
SOURCE AND  
DESTINATION  
SEGMENT  
MASK 1  
MASK 2  
COMMANDS &  
STATUS (16)  
COUNTERS  
/E  
/W  
/MA  
/MM  
INSTRUCTION (W/O)  
ADDRESS  
CAM ARRAY  
N
CONTROL  
NEXT FREE ADDRESS (R/O)  
CONTROL  
2N WORDS  
X 64 BITS  
/CM  
2
/RESET  
SEGMENT CONTROL  
PAGE ADDRESS (LOCAL)  
DEVICE SELECT (GLOBAL)  
STATUS (15-0) (R/O)  
16  
MATCH ADDR &  
/MA FLAG  
/EC  
N+1  
2
/FF  
/FI  
/MM, /FL  
MATCH  
AND  
FLAG  
STATUS (31-16) (R/O)  
REGISTER SET  
/MF  
/MI  
LOGIC  
Figure 1: LANCAM B Family Block Diagram  
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are  
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of  
MUSIC Semiconductors.  
April 18, 2005 Rev. 1  

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