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MT5C6408C-12L/IT PDF预览

MT5C6408C-12L/IT

更新时间： 2024-02-26 23:12:51
品牌 Logo 应用领域
MICROSS 静态存储器内存集成电路
页数 文件大小 规格书
12页 96K
描述
Standard SRAM, 8KX8, 12ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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中文翻译

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MT5C6408C-12L/IT 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP,针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.39
Is Samacsys：N最长访问时间：12 ns
JESD-30 代码：R-CDIP-T28内存密度：65536 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：28
字数：8192 words字数代码：8000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：8KX8
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：DIP
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：5.715 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

MT5C6408C-12L/IT 数据手册

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SRAM  
MT5C6408  
Austin Semiconductor, Inc.  
8K x 8 SRAM  
PIN ASSIGNMENT  
(Top View)  
SRAM MEMORY ARRAY  
AVAILABLE AS MILITARY  
28-Pin DIP (C)  
(300 MIL)  
28-Pin LCC (EC)  
SPECIFICATIONS  
• SMD 5962-38294  
• MIL-STD-883  
4 3  
2 1 28 27 26  
NC  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0 10  
DQ1 11  
DQ2 12  
DQ3 13  
Vss 14  
1
2
3
4
5
6
7
8
9
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Vcc  
WE\  
CE2  
A8  
A9  
A11  
OE\  
A10  
CE1\  
DQ8  
DQ7  
DQ6  
DQ5  
DQ4  
2 5  
2 4  
2 3  
2 2  
2 1  
A8  
A9  
A11  
OE\  
A10  
A5  
A4  
A3  
A2  
A1  
5
6
7
8
9
FEATURES  
• High Speed: 12, 15, 20, 25, 35, 45, 55, and 70ns  
• Battery Backup: 2V data retention  
• High-performance, low-power CMOS double-metal  
process  
A0 1 0  
DQ0 1 1  
2 0 CE1\  
1 9  
DQ7  
12 13 14 15 16 17 18  
• Single +5V (+10%) Power Supply  
• Easy memory expansion with CE1\ and CE2  
• All inputs and outputs are TTL compatible  
28-Pin Flat Pack (F)  
1
2 8  
2 7  
2 6  
2 5  
2 4  
2 3  
2 2  
2 1  
2 0  
1 9  
1 8  
1 7  
1 6  
1 5  
NC  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
Vcc  
WE\  
CE2  
A8  
A9  
A11  
OE\  
A10  
CE1\  
DQ8  
DQ7  
DQ6  
DQ5  
DQ4  
2
3
4
5
OPTIONS  
• Timing  
MARKING  
6
7
8
12ns access  
15ns access  
20ns access  
25ns access  
35ns access  
45ns access  
55ns access  
70ns access  
-12  
-15  
-20  
-25  
-35  
-45  
-55*  
-70*  
9
1 0  
1 1  
1 2  
1 3  
1 4  
A0  
DQ1  
DQ2  
DQ3  
Vss  
GENERAL DESCRIPTION  
The MT5C6408, 8K x 8 SRAM, employs high-speed,  
low-power CMOS technology, eliminating the need for clocks  
or refreshing. These SRAM’s have equal access and cycle  
times.  
For flexibility in high-speed memory applications,  
Austin Semiconductor offers dual chip enables (CE1\, CE2) and  
output enable (OE\) capability. These enhancements can place  
the outputs in High-Z for additional flexibility in system design.  
Writing to these devices is accomplished when write  
enable (WE\) and CE1\ inputs are both LOW and CE2 is HIGH.  
Reading is accomplished when WE\ and CE2 remain HIGH and  
CE1\ and OE\ go LOW. The device offers a reduced power  
standby mode when disabled. This allows system designs to  
achieve low standby power requirements.  
• Package(s)  
Ceramic DIP (300 mil)  
Ceramic LCC  
C
EC  
F
No. 108  
No. 204  
No. 302  
Ceramic Flatpack  
• Operating Temperature Ranges  
Industrial (-40oC to +85oC)  
Military (-55oC to +125oC)  
IT  
XT  
• 2V data retention/low power  
L
*Electrical characteristics identical to those provided for the  
45ns access devices.  
These devices operate from a single +5V power sup-  
ply and all inputs and outputs are fully TTL compatible.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
MT5C6408  
Rev. 3.0 2/01  
1
1234567...12

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