DRAM
MT4C4001J
Austin Semiconductor, Inc.
1 MEG x 4 DRAM
PIN ASSIGNMENT
(Top View)
Fast Page Mode DRAM
20-Pin DIP (C, CN)
20-Pin SOJ (ECJ),
AVAILABLE AS MILITARY
20 Vss
20-Pin LCC (ECN), &
20-Pin GullWing (ECG)
DQ1
DQ2
WE\
RAS\
A9
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
19 DQ4
18 DQ3
17 CAS\
16 OE\
15 A8
14 A7
13 A6
12 A5
11 A4
SPECIFICATIONS
• SMD 5962-90847
• MIL-STD-883
1
26
25
24
23
22
DQ1
DQ2
WE\
RAS\
A9
Vss
2
3
4
5
DQ4
DQ3
CAS\
OE\
FEATURES
• Industry standard x4 pinout, timing, functions, and
packages
9
18
17
16
15
14
A8
A7
A6
A5
A4
A0
A1
A2
A3
Vcc
10
11
12
13
• High-performance, CMOS silicon-gate process
• Single +5V±10% power supply
• Low-power, 2.5mW standby; 300mW active, typical
• All inputs, outputs, and clocks are fully TTL and CMOS
compatible
• 1,024-cycle refresh distributed across 16ms
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\
(CBR), and HIDDEN
Vcc 10
20-Pin DIP (CZ)
OE\
1
3
5
7
9
2
4
6
8
CAS\
DQ4
DQ1
WE\
DQ3
Vss
DQ2
RAS\
• FAST PAGE MODE access cycle
• CBR with WE\ a HIGH (JEDEC test mode capable via
WCBR)
10 A9
12 A1
14 A3
16 A4
18 A6
20 A8
A0 11
A2 13
Vcc 15
A5 17
A7 19
OPTIONS
• Timing
MARKING
70ns access
80ns access
100ns access
120ns access
-7
-8
-10
-12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles each bit is
uniquely addressed through the 20 address bits which are
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the
first 10 bits and CAS\ the later 10 bits. A READ or WRITE
cycle is selected with the WE\ input. A logic HIGH on WE\
dictates READ mode while a logic LOW on WE\ dictates
WRITE mode. During a WRITE cycle, data-in (D) is latched
by the falling edge of WE\ or CAS\, whichever occurs last. If
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)
remain open (High-Z) until the next CAS\ cycle. If WE\ goes
LOW after data reaches the output pin(s), Qs are activated and
retain the selected cell data as long as CAS\ remains low
(regardless of WE\ or RAS\). This LATE WE\ pulse results in
a READ-WRITE cycle. The four data inputs and four data
outputs are routed through four pins using common I/O and
pin direction is controlled by WE\ and OE\. FAST-PAGE-
MODE operations allow faster data operations (READ,
WRITE, or READ-MODIFY-WRITE) within a row address
(A0-A9) defined page boundary. The FAST PAGE MODE
(continued)
• Packages
Ceramic DIP (300 mil)
Ceramic DIP (400 mil)
Ceramic LCC*
Ceramic ZIP
Ceramic SOJ
CN
C
ECN
CZ
ECJ
ECG
No. 103
No. 104
No. 202
No. 400
No. 504
No. 600
Ceramic Gull Wing
*NOTE: If solder-dip and lead-attach is desired on LCC
packages, lead-attach must be done prior to the solder-
dip operation.
For more products and information
please visit our web site at
www.austinsemiconductor.com
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
MT4C4001J
Rev. 1.5 10/02
1