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MT4C4001JECG-12/XT PDF预览

MT4C4001JECG-12/XT

更新时间： 2024-01-29 09:22:22
品牌 Logo 应用领域
AUSTIN 内存集成电路动态存储器
页数 文件大小 规格书
20页 251K
描述
1 MEG x 4 DRAM Fast Page Mode DRAM

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MT4C4001JECG-12/XT 技术参数

生命周期：Lifetime Buy零件包装代码：SOIC
包装说明：CERAMIC PACKAGE-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.02风险等级：5.26
Is Samacsys：N访问模式：FAST PAGE
最长访问时间：120 ns其他特性：RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 代码：R-CDSO-G20长度：17.145 mm
内存密度：4194304 bit内存集成电路类型：FAST PAGE DRAM
内存宽度：4功能数量：1
端口数量：1端子数量：20
字数：1048576 words字数代码：1000000
工作模式：SYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：1MX4
封装主体材料：CERAMIC, METAL-SEALED COFIRED封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
认证状态：Not Qualified座面最大高度：3.556 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：8.89 mm
Base Number Matches：1

MT4C4001JECG-12/XT 数据手册

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DRAM  
MT4C4001J  
Austin Semiconductor, Inc.  
1 MEG x 4 DRAM  
PIN ASSIGNMENT  
(Top View)  
Fast Page Mode DRAM  
20-Pin DIP (C, CN)  
20-Pin SOJ (ECJ),  
AVAILABLE AS MILITARY  
20 Vss  
20-Pin LCC (ECN), &  
20-Pin GullWing (ECG)  
DQ1  
DQ2  
WE\  
RAS\  
A9  
A0  
A1  
A2  
A3  
1
2
3
4
5
6
7
8
9
19 DQ4  
18 DQ3  
17 CAS\  
16 OE\  
15 A8  
14 A7  
13 A6  
12 A5  
11 A4  
SPECIFICATIONS  
• SMD 5962-90847  
• MIL-STD-883  
1
26  
25  
24  
23  
22  
DQ1  
DQ2  
WE\  
RAS\  
A9  
Vss  
2
3
4
5
DQ4  
DQ3  
CAS\  
OE\  
FEATURES  
• Industry standard x4 pinout, timing, functions, and  
packages  
9
18  
17  
16  
15  
14  
A8  
A7  
A6  
A5  
A4  
A0  
A1  
A2  
A3  
Vcc  
10  
11  
12  
13  
• High-performance, CMOS silicon-gate process  
• Single +5V±10% power supply  
• Low-power, 2.5mW standby; 300mW active, typical  
• All inputs, outputs, and clocks are fully TTL and CMOS  
compatible  
• 1,024-cycle refresh distributed across 16ms  
• Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\  
(CBR), and HIDDEN  
Vcc 10  
20-Pin DIP (CZ)  
OE\  
1
3
5
7
9
2
4
6
8
CAS\  
DQ4  
DQ1  
WE\  
DQ3  
Vss  
DQ2  
RAS\  
• FAST PAGE MODE access cycle  
• CBR with WE\ a HIGH (JEDEC test mode capable via  
WCBR)  
10 A9  
12 A1  
14 A3  
16 A4  
18 A6  
20 A8  
A0 11  
A2 13  
Vcc 15  
A5 17  
A7 19  
OPTIONS  
• Timing  
MARKING  
70ns access  
80ns access  
100ns access  
120ns access  
-7  
-8  
-10  
-12  
GENERAL DESCRIPTION  
The MT4C4001J is a randomly accessed solid-state  
memory containing 4,194,304 bits organized in a x4  
configuration. During READ or WRITE cycles each bit is  
uniquely addressed through the 20 address bits which are  
entered 10 bits (A0-A9) at a time. RAS\ is used to latch the  
first 10 bits and CAS\ the later 10 bits. A READ or WRITE  
cycle is selected with the WE\ input. A logic HIGH on WE\  
dictates READ mode while a logic LOW on WE\ dictates  
WRITE mode. During a WRITE cycle, data-in (D) is latched  
by the falling edge of WE\ or CAS\, whichever occurs last. If  
WE\ goes LOW prior to CAS\ going LOW, the output pin(s)  
remain open (High-Z) until the next CAS\ cycle. If WE\ goes  
LOW after data reaches the output pin(s), Qs are activated and  
retain the selected cell data as long as CAS\ remains low  
(regardless of WE\ or RAS\). This LATE WE\ pulse results in  
a READ-WRITE cycle. The four data inputs and four data  
outputs are routed through four pins using common I/O and  
pin direction is controlled by WE\ and OE\. FAST-PAGE-  
MODE operations allow faster data operations (READ,  
WRITE, or READ-MODIFY-WRITE) within a row address  
(A0-A9) defined page boundary. The FAST PAGE MODE  
(continued)  
• Packages  
Ceramic DIP (300 mil)  
Ceramic DIP (400 mil)  
Ceramic LCC*  
Ceramic ZIP  
Ceramic SOJ  
CN  
C
ECN  
CZ  
ECJ  
ECG  
No. 103  
No. 104  
No. 202  
No. 400  
No. 504  
No. 600  
Ceramic Gull Wing  
*NOTE: If solder-dip and lead-attach is desired on LCC  
packages, lead-attach must be done prior to the solder-  
dip operation.  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.  
MT4C4001J  
Rev. 1.5 10/02  
1
1234567...20

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