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MSC1212Y3 PDF预览

MSC1212Y3

更新时间: 2024-01-13 02:26:00
品牌 Logo 应用领域
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页数 文件大小 规格书
69页 1095K
描述
Precision Analog-to-Digital Converter (ADC)

MSC1212Y3 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:TQFP-64针数:64
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:1 week
风险等级:0.69Is Samacsys:N
具有ADC:YES其他特性:ALSO OPERATES AT 2.7V MINIMUM SUPPLY
地址总线宽度:16位大小:8
边界扫描:NOCPU系列:8051
最大时钟频率:40 MHzDAC 通道:YES
DMA 通道:NO外部数据总线宽度:8
格式:FIXED POINTJESD-30 代码:S-PQFP-G64
JESD-609代码:e4长度:10 mm
低功率模式:YES湿度敏感等级:4
DMA 通道数量:I/O 线路数量:32
串行 I/O 数:13端子数量:64
计时器数量:4片上程序ROM宽度:8
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:TFQFP封装等效代码:TQFP64,.47SQ
封装形状:SQUARE封装形式:FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:3/5 V
认证状态:Not QualifiedRAM(字节):1280
RAM(字数):160ROM(单词):8192
ROM可编程性:FLASH座面最大高度:1.2 mm
速度:40 MHz子类别:Microcontrollers
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

MSC1212Y3 数据手册

 浏览型号MSC1212Y3的Datasheet PDF文件第4页浏览型号MSC1212Y3的Datasheet PDF文件第5页浏览型号MSC1212Y3的Datasheet PDF文件第6页浏览型号MSC1212Y3的Datasheet PDF文件第8页浏览型号MSC1212Y3的Datasheet PDF文件第9页浏览型号MSC1212Y3的Datasheet PDF文件第10页 
AC ELECTRICAL CHARACTERISTICS(1)(2): DVDD = 2.7V to 5.25V  
2.7V to 3.6V  
4.75V to 5.25V  
SYMBOL  
FIGURE  
PARAMETER  
MIN  
MAX  
MIN  
MAX  
UNITS  
System Clock  
(3)  
fOSC  
D
D
D
External Crystal Frequency (fOSC  
)
1
0
1
16  
16  
12  
1
1
1
30  
30  
12  
MHz  
MHz  
MHz  
(3)  
1/tOSC  
External Clock Frequency (fOSC)  
(3)  
fOSC  
External Ceramic Resonator Frequency (fOSC)  
Program Memory  
tLHLL  
A
A
A
A
A
A
A
A
A
A
A
ALE Pulse Width  
1.5tCLK 5  
0.5tCLK 10  
0.5tCLK  
1.5tCLK 5  
0.5tCLK 7  
0.5tCLK  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAVLL  
tLLAX  
tLLIV  
Address Valid to ALE LOW  
Address Hold After ALE LOW  
ALE LOW to Valid Instruction In  
ALE LOW to PSEN LOW  
2.5tCLK 35  
2tCLK 40  
2.5tCLK 25  
2tCLK 30  
tLLPL  
tPLPH  
tPLIV  
tPXIX  
tPXIZ  
tAVIV  
tPLAZ  
0.5tCLK  
0.5tCLK  
PSEN Pulse Width  
2tCLK 5  
2tCLK 5  
PSEN LOW to Valid Instruction In  
Input Instruction Hold After PSEN  
Input Instruction Float After PSEN  
Address to Valid Instruction In  
PSEN LOW to Address Float  
5
5  
tCLK 5  
3tCLK 40  
0
tCLK  
3tCLK 25  
0
Data Memory  
tRLRH  
B
B
RD Pulse Width (tMCS = 0)(4)  
RD Pulse Width (tMCS > 0)(4)  
2tCLK 5  
tMCS 5  
2tCLK 5  
tMCS 5  
ns  
ns  
tWLWH  
C
C
WR Pulse Width (tMCS = 0)(4)  
Pulse Width (tMCS > 0)(4)  
2tCLK 5  
tMCS 5  
2tCLK 5  
tMCS 5  
ns  
ns  
tRLDV  
B
B
RD LOW to Valid Data In (tMCS = 0)(4)  
RD LOW to Valid Data In (tMCS > 0)(4)  
2tCLK 40  
tMCS 40  
2tCLK 30  
tMCS 30  
ns  
ns  
tRHDX  
tRHDZ  
B
Data Hold After Read  
5  
5  
ns  
B
B
Data Float After Read (tMCS = 0)(4)  
Data Float After Read (tMCS > 0)(4)  
tCLK  
tCLK  
ns  
ns  
2tCLK  
2tCLK  
tLLDV  
tAVDV  
tLLWL  
tAVWL  
B
B
ALE LOW to Valid Data In (tMCS = 0)(4)  
ALE LOW to Valid Data In (tMCS > 0)(4)  
2.5tCLK 40  
2.5tCLK 25  
ns  
ns  
tCLK + tMCS 40  
tCLK + tMCS 25  
B
B
Address to Valid Data In (tMCS = 0)(4)  
Address to Valid Data In (tMCS > 0)(4)  
3tCLK 40  
3tCLK 25  
ns  
ns  
1.5tCLK + tMCS 40  
1.5tCLK + tMCS 25  
B, C  
B, C  
ALE LOW to RD or WR LOW (tMCS = 0)(4)  
ALE LOW to RD or WR LOW (tMCS > 0)(4)  
0.5tCLK 5  
tCLK 5  
0.5tCLK + 5  
tCLK + 5  
0.5tCLK 5  
tCLK 5  
0.5tCLK + 5  
tCLK + 5  
ns  
ns  
B, C  
B, C  
Address to RD or WR LOW (tMCS = 0)(4)  
Address to RD or WR LOW (tMCS > 0)(4)  
tCLK 5  
2tCLK 5  
tCLK 5  
2tCLK 5  
ns  
ns  
tQVWX  
tWHQX  
tRLAZ  
C
C
B
Data Valid to WR Transition  
Data Hold After WR  
8  
5  
ns  
ns  
ns  
tCLK 8  
tCLK 5  
RD LOW to Address Float  
0.5tCLK 5  
0.5tCLK 5  
tWHLH  
B, C  
B, C  
RD or WR HIGH to ALE HIGH (tMCS = 0)(4)  
RD or WR HIGH to ALE HIGH (tMCS > 0)(4)  
5  
tCLK 5  
5
5  
tCLK 5  
5
ns  
ns  
tCLK + 5  
tCLK + 5  
External Clock  
tHIGH  
D
D
D
D
HIGH Time(5)  
LOW Time(5)  
Rise Time(5)  
Fall Time(5)  
15  
15  
10  
10  
ns  
ns  
ns  
ns  
tLOW  
tR  
5
5
5
5
tF  
PSEN  
NOTES: (1) Parameters are valid over operating temperature range, unless otherwise specified. (2) Load capacitance for Port 0, ALE, and  
= 100pF,  
load capacitance for all other outputs = 80pF. (3) tCLK = 1/fOSC = one oscillator clock period for clock divider = 1. (4) tMCS is a time period related to the Stretch  
MOVX selection. The following table shows the value of tMCS for each stretch selection. (5) These values are characterized but not 100% production tested.  
MD2  
MD1  
MD0  
MOVX DURATION  
tMCS  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 Machine Cycles  
3 Machine Cycles (default)  
4 Machine Cycles  
5 Machine Cycles  
6 Machine Cycles  
7 Machine Cycles  
8 Machine Cycles  
9 Machine Cycles  
0
4tCLK  
8tCLK  
12tCLK  
16tCLK  
20tCLK  
24tCLK  
28tCLK  
MSC1212  
SBAS278A  
7
www.ti.com  

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