Datasheet > MC68SEC000AE20

MC68SEC000AE20

更新时间： 2024-02-07 01:06:53

品牌	Logo	应用领域
恩智浦 - NXP		PC
页数	文件大小	规格书
8页	250K
描述
8/16/32 BIT MPU, STATIC

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技术参数
数据手册

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MC68SEC000AE20 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	Reach Compliance Code：	unknown
风险等级：	5.71	Samacsys Confidence：	4
Samacsys Status：	Released	2D Presentation：	https://componentsearchengine.com/2D/0T/560335.1.1.png
Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=560335	PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=560335
3D View：	https://componentsearchengine.com/viewer/3D.php?partID=560335	Samacsys PartID：	560335
Samacsys Image：	https://componentsearchengine.com/Images/9/MC68SEC000AE20.jpg	Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/MC68SEC000AE20.jpg
Samacsys Pin Count：	64	Samacsys Part Category：	Integrated Circuit
Samacsys Package Category：	Quad Flat Packages	Samacsys Footprint Name：	MC68SEC000AE20
Samacsys Released Date：	2019-10-18 08:11:37	Is Samacsys：	N
Base Number Matches：	1

MC68SEC000AE20 数据手册

Freescale Semiconductor, Inc.

A23-A0

D15-D0

ADDRESS BUS

DATA BUS

GND

CLK

FC0

FC1

FC2

R/W

UDS

LDS

PROCESSOR

STATUS

ASYNCHRONOUS

BUS CONTROL

DTACK

MC68SEC000

BUS ARBITRATION

CONTROL

IPL0

IPL1

BERR

RESET

HALT

SYSTEM

CONTROL

INTERRUPT

CONTROL

IPL2

AVEC

MODE

Figure 2. Functional Signal Groups

Address Bus (A23-A0)

This 24-bit, unidirectional, three-state bus can address 16 Mbytes of data. It provides the address for bus

operation during all cycles except interrupt cycles. During interrupt cycles, A3, A2, and A1 reflect the level

of the interrupt being serviced, while A23-A4 and A0 are set to a logic high.

Data Bus (D15-D0)

This 16-bit, bidirectional, three-state bus is the general-purpose data path. Using the mode pin, you can

statically select either 8- or 16-bit modes for data transfer.

Asynchronous Bus Control

Asynchronous data transfers are handled using the following control signals: address strobe (AS), read/

write (R/W), upper and lower data strobes (UDS, LDS), and data transfer acknowledge (DTACK). The

address strobe signal indicates there is a valid address on the address bus. Read/write defines the data bus

transfer as a read or write cycle. The data strobes control the flow of data on the data bus and the data

transfer acknowledge indicates that the data transfer is complete.

Bus Arbitration Control

In multiple bus master systems, the bus arbitration circuit determines which device will be the bus master.

The bus request (BR) indicates that an external device requires bus mastership. A bus grant (BG) indicates

to all other potential bus master devices that the controller will release bus control at the end of the current

bus cycle.

MC68SEC000 PRODUCT INFORMATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

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