シングル/デュアル/クワッド、超高速、+ 3 V /+ 5 V
B eyond-the-R ailsコンパレータ
1–647/MAX9
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +5.5V, V = 0V, C
= 5pF, V = 0V, V = 0V, unless otherwise noted.) (Note 1)
SHDN LE
CC
CM
OUT
T
= +25°C
T
to T
A
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
4
MAX
MIN
MAX
Output Capacitance
pF
MAX961/MAX963, V = 5V
8.5
6.5
5
11
8
11
9
CC
Supply Current
per Comparator
I
CC
MAX962/MAX964, V = 5V
mA
CC
MAX997/MAX999, V = 5V
CC
6.5
6.5
Shutdown Supply Current
per Comparator
MAX961/MAX963/MAX964/
MAX997, V = 5V
CC
I
0.27
0.5
1
0.5
20
mA
µA
SHDN
MAX961/MAX963/MAX964/
Shutdown Output
Leakage Current
MAX997, V
= 0.5V and
OUT
V
- 0.5V
V = 5V
CC
CC
Rise/Fall Time
t , t
2.3
ns
V
R
F
(V / 2)
CC
+ 0.4
(V / 2)
CC
+ 0.4
Logic Input High
V
IH
(V / 2)
CC
- 0.4
(V / 2)
CC
- 0.4
Logic Input Low
V
IL
V
Logic Input Current
Propagation Delay
I , I
V
= 0V or V
CC
±15
7
±30
8.5
µA
ns
IL IH
LOGIC
t
5mV overdrive (Note 7)
4.5
0.3
0.3
PD
Between any two channels or
outputs (Q/Q)
Differential Propagation
Delay
t
ns
PD
Propagation-Delay Skew
Data-to-Latch Setup Time
Latch-to-Data Hold Time
Latch Pulse Width
t
Between t
and t
ns
ns
ns
ns
ns
SKEW
PD-
PD+
t
MAX961/MAX963 (Note 8)
MAX961/MAX963 (Note 8)
MAX961/MAX963 (Note 8)
MAX961/MAX963 (Note 8)
5
5
5
5
SU
t
H
t
5
5
LPW
Latch Propagation Delay
t
10
10
LPD
Delay until output is high-Z
(>10kΩ)
Shutdown Time
t
150
250
ns
ns
OFF
Shutdown Disable Time
t
Delay until output is valid
ON
Note 1: The MAX961EUA/MAX962EUA/MAX997EUA/MAX999EUK are 100% production tested at T = +25°C; all temperature specifica-
A
tions are guaranteed by design.
Note 2: Inferred by CMRR. Either input can be driven to the absolute maximum limit without false output inversion, provided that the other
input is within the input voltage range.
Note 3: The input-referred trip points are the extremities of the differential input voltage required to make the comparator output change
state. The difference between the upper and lower trip points is equal to the width of the input-referred hysteresis zone. (See
Figure 1.)
Note 4: Input offset voltage is defined as the mean of the trip points.
Note 5: CMRR = (V
- V
OSH
) / 5.2V, where V
is the offset at V = -0.1V and V
is the offset at V = 5.1V.
OSH CM
OSL
OSL
CM
Note 6: PSRR = (V 2.7 - V 5.5) / 2.8V, where V 2.7 is the offset voltage at V = 2.7V, and V 5.5 is the offset voltage at
OS
OS
OS
CC
OS
V
CC
= 5.5V.
Note 7: Propagation delay for these high-speed comparators is guaranteed by design characterization because it cannot be accurately
measured using automatic test equipment. A statistically significant sample of devices is characterized with a 200mV step and
100mV overdrive over the full temperature range. Propagation delay can be guaranteed by this characterization, since DC tests
ensure that all internal bias conditions are correct. For low overdrive conditions, V
is added to the overdrive.
TRIP
Note 8: Guaranteed by design.
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