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MAX7313DAEG+T

更新时间： 2024-01-11 12:42:04

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
26页	248K
描述
Parallel I/O Port, CMOS,

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技术参数
数据手册

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MAX7313DAEG+T 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	,	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
Factory Lead Time：	10 weeks	风险等级：	5.78
峰值回流温度（摄氏度）：	NOT SPECIFIED	技术：	CMOS
处于峰值回流温度下的最长时间：	NOT SPECIFIED	uPs/uCs/外围集成电路类型：	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：	1

MAX7313DAEG+T 数据手册

16-Port I/O Expander with LED Intensity

Control, Interrupt, and Hot-Insertion Protection

MAX713

ELECTRICAL CHARACTERISTICS (continued)

, unless otherwise noted. Typical values are at V+ = 3.3V, T = + 25°C.)

MAX A

(Typical Operating Circuit, V+ = 2V to 3.6V, T = T

to T

MIN

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

= +25°C

0.15

0.26

0.3

V+ = 2V, I

= 20mA

= -40°C to +85°C

SINK

= T

to T

0.32

0.23

MIN

MAX

= +25°C

= -40°C to +85°C

= T to T

0.13

0.12

Output Low Voltage

P0–P15, INT/O16

V+ = 2.5V, I

= 20mA

0.26

0.28

0.23

0.24

0.26

0.4

SINK

MIN

MAX

= +25°C

= -40°C to +85°C

= T to T

V+ = 3.3V, I

MIN

MAX

Output Low-Voltage SDA

PWM Clock Frequency

= 6mA

OLSDA

SINK

kHz

PWM

TIMING CHARACTERISTICS

(Typical Operating Circuit, V+ = 2V to 3.6V, T = T

to T , unless otherwise noted. Typical values are at V+ = 3.3V, T = +25°C.)

MAX A

MIN

(Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Serial Clock Frequency

400

kHz

SCL

Bus Free Time Between a STOP and a START

Condition

1.3

µs

BUF

Hold Time, Repeated START Condition

Repeated START Condition Setup Time

STOP Condition Setup Time

Data Hold Time

0.6

µs

HD, STA

SU, STA

SU, STO

HD, DAT

(Note 2)

0.9

Data Setup Time

180

1.3

0.7

SU, DAT

SCL Clock Low Period

LOW

SCL Clock High Period

HIGH

20 +

Rise Time of Both SDA and SCL Signals, Receiving

Fall Time of Both SDA and SCL Signals, Receiving

Fall Time of SDA Transmitting

(Notes 3, 4)

(Notes 2, 3, 5)

300

250

0.1C

20 +

0.1C

20 +

F.TX

0.1C

Pulse Width of Spike Suppressed

Capacitive Load for Each Bus Line

(Notes 2, 6)

(Notes 2, 3)

400

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