Datasheet > MAX3874AETJ+D

MAX3874AETJ+D

更新时间： 2024-01-22 00:18:21

品牌	Logo	应用领域
美信 - MAXIM		/
页数	文件大小	规格书
17页	1120K
描述
Clock Recovery Circuit, 1-Func, Bipolar, 5 X 5 MM, 0.80 MM HEIGHT, ROHS COMPLIANT, MO-220WHHD-2, TQFN-32

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MAX3874AETJ+D 数据手册

2.488Gbps/2.667Gbps Clock and

Data Recovery with Limiting Amplifier

DC ELECTRICAL CHARACTERISTICS (continued)

= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V

= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)

CC A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LREF, RATESET, FREFSET)

LVTTL Input High Voltage

LVTTL Input Low Voltage

LVTTL Input Current

2.0

0.8

-10

2.4

+10

µA

LVTTL Output High Voltage

LVTTL Output Low Voltage

= +20µA

= -1mA

0.4

Note 1: At -40°C, DC characteristics are guaranteed by design and characterization.

Note 2: CML outputs open.

Note 3: Voltage applied to V

pin is from 0.3V to 2.1V when input threshold is adjusted from +170mV to -170mV.

CTRL

Note 4: R = 50Ω to V

AC ELECTRICAL CHARACTERISTICS

= +3.0V to +3.6V, T = -40°C to +85°C. Typical values at V

= +3.3V, T = +25°C, unless otherwise noted.) (Note 5)

CC A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

2.488

2.667

2.0212

MAX

UNITS

MAX3874 (RATESET = GND)

MAX3874 (RATESET = VCC)

MAX3874A

Serial Input Data Rate

Gbps

Differential Input Voltage (SDI )

Differential Input Voltage (SLBI )

Threshold adjust disabled, Figure 1 (Note 6)

BER ≤ 10^-10

1600

800

2.0

P-P

MAX3874

1.5

0.7

Jitter Transfer Bandwidth

Jitter Peaking

MHz

MAX3874A

f ≤ J

0.1

f = 100kHz

3.1

8.0

0.93

0.65

>0.5

>0.3

7.1

Sinusoidal Jitter Tolerance

(MAX3874)

f = 1MHz

0.62

0.44

P-P

f = 10MHz

f = 1MHz (Note 7)

f = 10MHz (Note 7)

f = 100kHz

Sinusoidal Jitter Tolerance

(MAX3874A)

Sinusoidal Jitter Tolerance with

Threshold Adjust Enabled

(Note 8)

f = 1MHz

0.82

0.54

2.7

f = 10MHz

mUI

Jitter Generation

(Note 9)

4.0

RMS

GEN

100kHz to 2.5GHz

2.5GHz to 4GHz

Differential Input Return Loss

(SDI±, SLBI±)

-20log

| S

CML OUTPUT SPECIFICATION (SDO±, SCLKO±)

Output Edge Speed

t , t

20% to 80%

110

1000

+40

CML Output Differential Swing

Clock-to-Q Delay

R = 100Ω differential

600

-40

800

P-P

(Note 10)

CLK-Q

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