2.125Gbps, 3.3V
Quad-Port Bypass with Repeater
CF
CLKEN
CFM
CFP
TTLIN
LOCK
LOCKEN
D1
D0
CDR
CLK
EN
DIN DOUT
Q
OUT+
OUT-
IN+
IN-
D0 Q
D1
D0 Q
D1
D0 Q
D1
D0 Q
D1
D0 Q
D1
V
CC
GND
MAX3752
TTLIN
TTLIN
TTLIN
TTLIN
TTLIN
CDREN
SEL1
SEL2
SEL3
SEL4
Figure 1. Functional Diagram
clock signal is available for test purposes at LOUT1 (the
output of the first port bypass circuit) when the clock
enable input (CLKEN) is set to a TTL high level. A TTL
low on CDREN disables the CDR and connects the
input buffer output directly to the port bypass circuits.
Detailed Description
The MAX3752 quad PBC consists of an input buffer, a
clock/data recovery circuit (for optional data recovery),
four serially connected port bypass circuits, and an
output buffer (Figure 1). The circuit design is optimized
for both high-speed (2Gbps) and low-voltage (+3.3V)
operation.
Port Bypass Circuits
The output of the 2:1 input multiplexer drives a cascad-
ed series of four PBCs. Each PBC consists of a differen-
tial output buffer, a differential input buffer, and a 2:1
multiplexer. The multiplexer select input (SELn) controls
which multiplexer input is connected to the multiplexer
output. A TTL low on the multiplexer select pin causes
the data signal from the previous stage to be connected
to the multiplexer output (port bypass mode). A TTL
high on the multiplexer select pin causes the data signal
from the input buffer to be connected to the multiplexer
output (port enable mode). The output of the last PBC
drives the output buffer.
Input Buffer
The input buffer provides line termination and level con-
version. It accepts a differential input voltage of 200mV
to 2200mV at the IN+ and IN- pins. Internal resistors
terminate each input to 75Ω (150Ω total between the
two inputs), eliminating the need for external termina-
tion resistors in most applications (see Applications
Information for a suggested interface to 50Ω systems).
Clock and Data Recovery
The purpose of the clock and data recovery (CDR) is to
improve jitter transfer performance by attenuating jitter
that may be present in the input data. The CDR can
recover data signals that are corrupted by up to 0.7UI
of high-frequency jitter (BER = 10-12). When data recov-
ery is not needed, the CDR may be disabled in order to
save power.
Output Buffer
The output signal of the last PBC drives the differential
high-power output buffer. The output buffer drives the
output port (OUT ). Internal resistors terminate each
output to 75Ω (150Ω total between the two outputs),
eliminating the need for external termination resistors in
most applications (see Applications Information for a
suggested interface to 50Ω systems). The output buffer
produces a differential output voltage of 1000mV to
1600mV when driving a differential 150Ω load.
The input buffer drives the CDR circuit, as well as one
input of a 2:1 multiplexer. A TTL high on the CDR enable
pin (CDREN) enables the CDR and connects the CDR
data output to the port bypass circuits. The recovered
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