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MAX367CWN+ PDF预览

MAX367CWN+

更新时间: 2024-02-13 18:20:34
品牌 Logo 应用领域
美信 - MAXIM 电路保护
页数 文件大小 规格书
12页 104K
描述
SPST, 8 Func, 1 Channel, CMOS, PDSO18, 0.300 INCH, SOP-18

MAX367CWN+ 技术参数

是否无铅: 不含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:0.300 INCH, CERDIP-18针数:18
Reach Compliance Code:unknown风险等级:5.29
其他特性:SIGNAL LINE CIRCUIT PROTECTOR模拟集成电路 - 其他类型:SPST
JESD-30 代码:R-GDIP-T18JESD-609代码:e0
湿度敏感等级:1标称负供电电压 (Vsup):-15 V
信道数量:1功能数量:8
端子数量:18最大通态电阻 (Ron):100 Ω
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):245座面最大高度:5.08 mm
最大供电电压 (Vsup):18 V最小供电电压 (Vsup):2.25 V
标称供电电压 (Vsup):15 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:TIN LEAD端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

MAX367CWN+ 数据手册

 浏览型号MAX367CWN+的Datasheet PDF文件第2页浏览型号MAX367CWN+的Datasheet PDF文件第3页浏览型号MAX367CWN+的Datasheet PDF文件第4页浏览型号MAX367CWN+的Datasheet PDF文件第6页浏览型号MAX367CWN+的Datasheet PDF文件第7页浏览型号MAX367CWN+的Datasheet PDF文件第8页 
S ig n a l-Lin e Circ u it P ro t e c t o rs  
/MAX367  
______________________________________________________________P in De s c rip t io n  
PIN  
NAME*  
FUNCTION  
MAX366  
MAX367  
1, 2, 3  
4–8  
1, 2, 3  
IN1, IN2, IN3  
IN4–IN8  
Signal Inputs 1, 2, 3  
4
Signal Inputs 4–8  
9
V-  
Negative Supply Voltage Input  
Signal Outputs 4–8  
10–14  
OUT8–OUT4  
OUT3, OUT2,  
OUT1  
5, 6, 7  
8
15, 16, 17  
18  
Signal Outputs 1, 2, 3  
V+  
Positive Supply Voltage Input  
* Inputs and outputs are names for convenience only; inputs and outputs are identical and interchangeable.  
___________Ba c k g ro u n d In fo rm a t io n  
_______________De t a ile d De s c rip t io n  
When a voltage outside the supply range is applied to  
most integrated circuits, there is a strong possibility they  
will be damaged or latch up” (that is, fail to operate prop-  
erly even after the offending voltage is removed). If an  
ICs input or output pin is supplied with a voltage when the  
ICs power is off, and power is subsequently applied, the  
device may act as an SCR and destroy itself and/or other  
circuitry. Such faults” are commonly encountered in  
modular control systems where power and signals to inter-  
connected modules may be interrupted and re-estab-  
lished at random. They can happen during production  
testing, maintenance, start-up, or a power brownout.”  
In t e rn a l Co n s t ru c t io n  
Figure 1 shows the simplified internal construction of  
each protector inside the MAX366/MAX367. Each circuit  
consists of two N-channel FETs and one P-channel FET.  
All the FETs are enhancement types; that is, the N chan-  
nels must have approximately 1.3V of positive gate volt-  
age in order to conduct, and the P channel must have  
approximately 2V of negative gate voltage in order to  
conduct.  
During normal operation, V+ is connected to a positive  
potential and V- is connected to a negative potential.  
Since their gates are tied to V+, transistors Q1 and Q3  
conduct as long as their sources are at least 1.3V below  
V+ (the N-channel gate threshold.) Transistor Q2s gate  
is tied to V-, so it conducts as long as its source is 2V or  
more above V- (the P-channel gate threshold.)  
The MAX366/MAX367 are designed to protect delicate  
input and output circuitry from overvoltage faults up to  
±40V (with or without power applied), in devices such as  
op amps, analog-to-digital/digital-to-analog converters,  
and voltage references. These circuit protectors automati-  
cally limit signal voltages and currents to safe levels with-  
out degrading normal signal performance, even in very  
high-impedance circuits. They are powered by the power  
supply of the protected circuit and inserted into the signal  
lines. There are no control lines, programming pins, or  
adjustments.  
V-  
P
IN  
OUT  
Unlike shunt diode networks, these devices are low-  
impedance FETs that become high impedance during a  
fault condition, so fault current and power dissipation are  
extremely low. Equally important, leakage current during  
normal and fault conditions is extremely low. In addition,  
unlike most discrete networks, these parts protect circuits  
both when power is off and during power transitions.  
Q2  
N
N
Q1  
Q3  
V+  
Figure 1. Simplified Internal Structure  
_______________________________________________________________________________________  
5

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