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MAX2602ESA-T

更新时间: 2024-01-02 07:16:14
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美信 - MAXIM 晶体晶体管
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6页 84K
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MAX2602ESA-T 数据手册

 浏览型号MAX2602ESA-T的Datasheet PDF文件第1页浏览型号MAX2602ESA-T的Datasheet PDF文件第2页浏览型号MAX2602ESA-T的Datasheet PDF文件第3页浏览型号MAX2602ESA-T的Datasheet PDF文件第4页浏览型号MAX2602ESA-T的Datasheet PDF文件第6页 
3.6V, 1W RF Power Transistors  
for 900MHz Applications  
1/MAX602  
Slug Layout Techniques  
Applications Information  
The most important connection to make to the  
MAX2601/MAX2602 is the back side. It should connect  
directly to the PC board ground plane if it is on the top  
side, or through numerous plated through-holes if the  
ground plane is buried. For maximum gain, this con-  
nection should have very little self-inductance. Since it  
is also the thermal path for heat dissipation, it must  
have low thermal impedance, and the ground plane  
should be large.  
Optimum Port Impedance  
The source and load impedances presented to the  
MAX2601/MAX2602 have a direct impact upon its gain,  
output power, and linearity. Proper source- and load-  
terminating impedances (Z and Z ) presented to the  
S
L
power transistor base and collector will ensure optimum  
performance.  
For a power transistor, simply applying the conjugate of  
the transistor’s input and output impedances calculated  
from small-signal S-parameters will yield less than opti-  
mum device performance.  
For maximum efficiency at V  
= 0.75V and V  
=
CC  
BB  
3.6V, the optimum power-transistor source and load  
impedances (as defined in Figure 3) are:  
4
3
2
1
At 836MHz: Z = 5.5 + j2.0  
S
MAX2601  
MAX2602  
Z = 6.5 + j1.5  
L
2.8nH  
2.8nH  
2.8nH  
At 433MHz: Z = 9.5 - j2.5  
S
Z = 8.5 - j1.5  
L
Z
and Z reflect the impedances that should be pre-  
L
S
sented to the transistor’s base and collector. The pack-  
age parasitics are dominated by inductance (as shown  
in Figure 3), and need to be accounted for when calcu-  
2.8nH  
Z
S
Z
L
lating Z and Z .  
S
L
5
6
7
8
The internal bond and package inductances shown  
in Figure 3 should be included as part of the end-  
application matching network, depending upon exact  
layout topology.  
Figure 3. Optimum Port Impedance  
Package Information  
For the latest package outline information and land patterns, go  
to www.maxim-ic.com/packages.  
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.  
8 SOIC  
S8E-12  
21-0041  
_______________________________________________________________________________________  
5

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