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MAX1005EEE

更新时间： 2024-02-07 10:21:22
品牌 Logo 应用领域
美信 - MAXIM 模拟IC信号电路光电二极管
页数 文件大小 规格书
8页 97K
描述
IF Undersampler

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MAX1005EEE 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：0.150 INCH, 0.025 INCH PITCH, QSOP-16针数：16
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.06Is Samacsys：N
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-PDSO-G16
JESD-609代码：e0长度：4.89 mm
湿度敏感等级：1功能数量：1
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：245
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2.7 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
Base Number Matches：1

MAX1005EEE 数据手册

 浏览型号MAX1005EEE的Datasheet PDF文件第1页浏览型号MAX1005EEE的Datasheet PDF文件第2页浏览型号MAX1005EEE的Datasheet PDF文件第3页浏览型号MAX1005EEE的Datasheet PDF文件第5页浏览型号MAX1005EEE的Datasheet PDF文件第6页浏览型号MAX1005EEE的Datasheet PDF文件第7页 
IF Un d e rs a m p le r  
ELECTRICAL CHARACTERISTICS (continued)  
(VCCA = VCCD = 3.0V, f  
= 15MHz, R = ∞, T = T  
to T , unless otherwise noted.)  
MAX  
CLK  
L
A
MIN  
PARAMETER  
SYMBOL  
CONDITIONS
MIN  
TYP  
MAX  
7
UNITS  
µA  
D0–D6, CLK; VCCD = 2.7V to 5.5V  
-1  
TXEN = RXEN  
RXEN, TXEN;  
±1  
VCCD = 2.7V  
to 3.6V  
TXEN = 0 and RXEN = 1, or  
TXEN = 1 and RXEN = 0  
±2  
±1  
±4  
8
Input Current  
I
IN  
MAX105  
TXEN = RXEN  
RXEN, TXEN;  
VCCD = 3.6V  
to 5.5V  
TXEN = 0 and RXEN = 1, or  
TXEN = 1 and RXEN = 0  
Input Capacitance  
C
D0–D6, CLK; TXEN = 1, RXEN = 0 (Note 6)  
pF  
IN  
TIMING CHARACTERISTICS (Data Outputs: R = 1MΩ, C = 15pF, T = T  
to T , unless otherwise noted.) (Note 12)  
MAX  
L
L
A
MIN  
DAC Data Setup Time  
DAC Data Hold Time  
CLK Duty Cycle  
t
T
= +25°C (Note 6)  
5
5
0.6  
0.3  
ns  
ns  
%
DS  
A
t
T
A
= +25°C (Note 6)  
HOLD  
45  
55  
20  
ADC CLK to Output Data Valid  
t
C
≤ 12.5pF  
L
13  
ns  
DO  
Note 1: TXEN = 1, RXEN = 0. All DAC transfer function parameters are measured differentially from AIO+ to AIO- using the End-  
Point Linearity method.  
Note 2:  
f
IN  
= 4.3MHz digital sine wave applied to DAC data inputs; f  
= 15MHz. The reference frequency (f ) is defined to be  
REF  
CLK  
10.7MHz (f  
- f ). All frequency components present in the DAC output waveform except for f  
and f are consid-  
REF IN  
CLK IN  
ered spurious.  
Note 3: For DAC SFDR measurements, the amplitude of f  
(10.7MHz) is compared to the amplitudes of all frequency compo-  
REF  
nents of the output waveform except for f (4.3MHz).  
IN  
Note 4: For DAC measurements, THD+N is defined as the ratio of the square-root of the sum-of-the-squares of the RMS values of  
all harmonic and noise components of the output waveform (except for f and f  
IN  
) to the RMS amplitude of the f  
com-  
REF  
REF  
ponent.  
Note 5: Clock feedthrough is defined as the difference in amplitude between the f  
measured differentially from AIO+ to AIO-.  
component and the f  
component when  
REF  
CLK  
Note 6: Guaranteed by design. Not production tested.  
Note 7: The DAC input interface is a master/slave register. An additional half clock cycle is required for data at the digital inputs to  
propagate through to the DAC switches.  
Note 8: RXEN = 1, TXEN = 0. Unless otherwise noted, for all receive ADC measurements, the analog input signal is applied differ-  
entially from AIO+ to AIO-, specified using the Best-Fit Straight-Line Linearity method.  
Note 9:  
f
IN  
= 10.7MHz, f  
= 15MHz. Amplitude is 1dB below full-scale. The reference frequency (f ) is defined to be 4.3MHz  
REF  
CLK  
(f  
- f ). All components except for f  
and f are considered spurious.  
REF IN  
CLK IN  
Note 10: Receive ADC THD measurements include the first five harmonics.  
Note 11: CAUTION: Operation of the analog inputs AIO+ and AIO- (pins 4 and 5) at more than 1.5V below VCCA could cause  
latchup and possible destruction of the part. Avoid shunt capacitances to GND on these pins. If shunt capacitances are  
required, then bypass these pins only to VCCA.  
Note 12: All digital input signals are measured from 50% amplitude reference points. All digital output signal propagation delays are  
measured to V  
for rising output signals and to V  
for falling output signals. The values for V and V  
OH(AC) OL(AC)  
OH(AC)  
OL(AC)  
as a function of the VCCD supply are shown in the following table:  
VCCD (V)  
2.7 to 3.3  
3.3 to 5.5  
V
(V)  
V
(V)  
OL(AC)  
OH(AC)  
VCCD - 1.1  
2/3 x VCCD  
0.5  
0.5  
4
_______________________________________________________________________________________  
12345678

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