Datasheet > 可编程逻辑 > 可编程逻辑器件> M5-192/104-12HI

M5-192/104-12HI

更新时间： 2024-02-26 00:35:52

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
47页	1092K
描述
Fifth Generation MACH Architecture

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

M5-192/104-12HI 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
Reach Compliance Code：	unknown	风险等级：	5.72
Is Samacsys：	N	其他特性：	YES
最大时钟频率：	71 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G144	JESD-609代码：	e0
JTAG BST：	YES	专用输入次数：
I/O 线路数量：	104	宏单元数：	192
端子数量：	144	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	0 DEDICATED INPUTS, 104 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装等效代码：	QFP144,1.2SQ
封装形状：	SQUARE	封装形式：	FLATPACK
电源：	5 V	可编程逻辑类型：	EE PLD
传播延迟：	18 ns	认证状态：	Not Qualified
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.635 mm
端子位置：	QUAD	Base Number Matches：	1

M5-192/104-12HI 数据手册

Advanced power management options allow designers to incrementally reduce power while

maintaining the level of performance needed for today’s complex designs. I/O safety features

allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system

programmable through an IEEE 1149.1 Test Access Port (TAP) interface.

FUNCTIONAL DESCRIPTION

The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block

interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the

block interconnect is called a segment. The second level of interconnect, the segment

interconnect, ties all of the segments together. The only logic difference between any two MACH

5 devices is the number of segments. Therefore, once a designer is familiar with one device,

consistent performance can be expected across the entire family. All devices have four clock pins

available which can also be used as logic inputs.

CLK

Block:

16 MCs

Segment:

4 Blocks

Segment Interconnect

20446G-001

Figure 1. MACH 5 Block Diagram

The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block

resembles an independent PAL device, it has superior control and logic generation capabilities.

I/O cells

Product-term array and Logic Allocator

Macrocells

Output enable generator

I/O Cells

The I/Os associated with each PAL block have a path directly back to that PAL block called local

feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect

line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment

interconnects provide connections between any two signals in a device. The block feeder assigns

block interconnect lines and local feedback lines to the PAL block inputs.

MACH 5 Family

1 2 345 6 7...47

下载PDF

与M5-192/104-12HI相关器件

型号	品牌	描述	获取价格	数据表
M5-192/104-12VC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12VI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12YC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-12YI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-15AC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5-192/104-15AI	LATTICE	Fifth Generation MACH Architecture	获取价格

与M5-192/104-12HI相关文章

STM32F030C6芯片介绍：主要参数分析、引脚配置说明、功耗及封装
2024-05-11

7
PCF8591数据手册解读：参数、引脚说明
2024-05-11

13
一文带你了解ss8050参数、引脚配置、应用指南
2024-05-11

6
深入解析AD7606高性能多通道模数转换器：资料手册参数分析
2024-05-10

9

产品中心

服务支持

精选活动

关于我们

帮助中心

M5-192/104-12HI

M5-192/104-12HI 技术参数

M5-192/104-12HI 数据手册

与M5-192/104-12HI相关器件

与M5-192/104-12HI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

M5-192/104-12HI

M5-192/104-12HI 技术参数

M5-192/104-12HI 数据手册

与M5-192/104-12HI相关器件

与M5-192/104-12HI相关文章

您还可以找

您在本页遇到什么问题？