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M5-192/104-10HI PDF预览

M5-192/104-10HI

更新时间: 2024-02-26 06:01:48
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑输入元件时钟
页数 文件大小 规格书
47页 1092K
描述
Fifth Generation MACH Architecture

M5-192/104-10HI 技术参数

是否Rohs认证: 不符合生命周期:Transferred
Reach Compliance Code:unknown风险等级:5.72
Is Samacsys:N其他特性:YES
最大时钟频率:83 MHz系统内可编程:YES
JESD-30 代码:S-PQFP-G144JESD-609代码:e0
JTAG BST:YES专用输入次数:
I/O 线路数量:104宏单元数:192
端子数量:144最高工作温度:85 °C
最低工作温度:-40 °C组织:0 DEDICATED INPUTS, 104 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装等效代码:QFP144,1.2SQ
封装形状:SQUARE封装形式:FLATPACK
电源:5 V可编程逻辑类型:EE PLD
传播延迟:16 ns认证状态:Not Qualified
子类别:Programmable Logic Devices最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.635 mm
端子位置:QUADBase Number Matches:1

M5-192/104-10HI 数据手册

 浏览型号M5-192/104-10HI的Datasheet PDF文件第2页浏览型号M5-192/104-10HI的Datasheet PDF文件第3页浏览型号M5-192/104-10HI的Datasheet PDF文件第4页浏览型号M5-192/104-10HI的Datasheet PDF文件第6页浏览型号M5-192/104-10HI的Datasheet PDF文件第7页浏览型号M5-192/104-10HI的Datasheet PDF文件第8页 
2
OE Generator  
Control Generator  
32  
32  
Block  
Feeder  
16  
Product-term  
Array  
Input Register  
Path  
2
32  
Interconnect Feeder  
20446G-002  
Figure 2. PAL Block Structure  
Product-Term Array and Logic Allocator  
The product-term array uses the same sum-of-products architecture as PAL devices and consists of  
32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluster is a sum-  
of-products function with either 3 of 4 product terms.  
Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of  
three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If  
only three product terms in a cluster are steered, the fourth can be used as an input to an XOR  
gate for separate logic generation and/or polarity control.  
The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output  
switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic  
allocation scheme in the MACH 5 device allows for the implementation of large equations (up to  
32 product terms) with only one pass through the logic array.  
Table 4. Product Term Steering Options for PT Clusters and Macrocells  
Macrocell  
Available Clusters  
C , C , C , C , C  
Macrocell  
Available Clusters  
C , C , C , C , C , C , C , C  
10 11 12  
M
M
8
0
0
1
2
3
4
5
6
7
8
9
M
C , C , C , C , C , C  
M
C , C , C , C , C , C , C , C  
6 7 8 9 10 11 12 13  
1
0
1
2
3
4
5
9
M
C , C , C , C , C , C , C  
M
C , C , C , C , C , C , C , C  
7 8 9 10 11 12 13 14  
2
0
1
2
3
4
5
6
10  
M
C , C , C , C , C , C , C , C  
M
C , C , C , C , C , C , C , C  
8 9 10 11 12 13 14 15  
3
0
1
2
3
4
5
6
7
11  
M
C , C , C , C , C , C , C , C  
M
C , C , C , C , C , C , C , C  
8 9 10 11 12 13 14 15  
4
0
1
2
3
4
5
6
7
12  
M
C , C , C , C , C , C , C , C  
M
C , C , C , C , C , C , C  
9 10 11 12 13 14 15  
5
1
2
3
4
5
6
7
8
13  
M
C , C , C , C , C , C , C , C  
M
C , C , C , C , C , C  
10 11 12 13 14 15  
6
2
3
4
5
6
7
8
9
14  
M
C , C , C , C , C , C , C , C  
M
C , C , C , C , C  
11 12 13 14 15  
7
3
4
5
6
7
8
9
10  
15  
MACH 5 Family  
5

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