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M27C400-80XF6 PDF预览

M27C400-80XF6

更新时间: 2024-02-08 08:40:18
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 可编程只读存储器电动程控只读存储器内存集成电路
页数 文件大小 规格书
14页 132K
描述
256KX16 UVPROM, 80ns, CDIP40, FRIT SEALED, WINDOWED, CERAMIC, DIP-40

M27C400-80XF6 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:FRIT SEALED, WINDOWED, CERAMIC, DIP-40
针数:40Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.61
风险等级:5.89最长访问时间:80 ns
备用内存宽度:8I/O 类型:COMMON
JESD-30 代码:R-GDIP-T40JESD-609代码:e0
长度:52.195 mm内存密度:4194304 bit
内存集成电路类型:UVPROM内存宽度:16
功能数量:1端子数量:40
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX16
输出特性:3-STATE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:WDIP封装等效代码:DIP40,.6
封装形状:RECTANGULAR封装形式:IN-LINE, WINDOW
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:5.97 mm最大待机电流:0.0001 A
子类别:EPROMs最大压摆率:0.07 mA
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:15.24 mm
Base Number Matches:1

M27C400-80XF6 数据手册

 浏览型号M27C400-80XF6的Datasheet PDF文件第1页浏览型号M27C400-80XF6的Datasheet PDF文件第3页浏览型号M27C400-80XF6的Datasheet PDF文件第4页浏览型号M27C400-80XF6的Datasheet PDF文件第5页浏览型号M27C400-80XF6的Datasheet PDF文件第6页浏览型号M27C400-80XF6的Datasheet PDF文件第7页 
M27C400  
Figure 2. DIP Connections  
Table 1. Signal Names  
A0-A17  
Q0-Q7  
Q8-Q14  
Q15A–1  
E
Address Inputs  
A17  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
E
1
40 A8  
Data Outputs  
2
39 A9  
3
38 A10  
37 A11  
36 A12  
35 A13  
34 A14  
33 A15  
32 A16  
31 BYTEV  
Data Outputs  
4
Data Output / Address Input  
Chip Enable  
5
6
7
8
G
Output Enable  
9
BYTEV  
Byte Mode / Program Supply  
Supply Voltage  
10  
11  
12  
PP  
PP  
M27C400  
V
30  
V
SS  
SS  
G
V
CC  
SS  
29 Q15A–1  
Q0 13  
Q8 14  
Q1 15  
Q9 16  
Q2 17  
Q10 18  
Q3 19  
Q11 20  
28 Q7  
V
Ground  
27 Q14  
26 Q6  
25 Q13  
24 Q5  
logically regarded as 16 bit wide, but read in the  
Byte-wide organisation, then with A–1 at V the  
lower 8 bits of the 16 bit data are selected and with  
IL  
23 Q12  
22 Q4  
A–1 at V the upper 8 bits of the 16 bit data are  
IH  
selected.  
21  
V
CC  
The M27C400 has two control functions, both of  
which must be logically active in order to obtain  
data at the outputs. In addition the Word-wide or  
Byte- wide organisation must be selected.  
AI01635  
Chip Enable (E) is the power control and should be  
used for device selection. Output Enable (G) is the  
output control and should be used to gate data to  
the output pins independent of device selection.  
Assuming that the addresses are stable, the ad-  
DEVICE OPERATION  
The operating modes of the M27C400 are listed in  
the Operating Modes Table. A single power supply  
is required in the read mode. All inputs are TTL  
compatible except for V and 12V on A9 for the  
Electronic Signature.  
PP  
dress access time (t  
) is equal to the delay  
). Data is available at the  
AVQV  
from E to output (t  
ELQV  
output after a delay of t  
from the falling edge  
Read Mode  
GLQV  
of G, assuming that E has been low and the ad-  
The M27C400 has two organisations, Word-wide  
and Byte-wide. The organisation is selected by the  
dresses have been stable for at least t  
-t  
.
AVQV GLQV  
signal level on the BYTEV pin. When BYTEV  
Standby Mode  
PP  
PP  
is at V the Word-wide organisation is selected  
and the Q15A–1 pin is used for Q15 Data Output.  
IH  
The M27C400 has a standby mode which reduces  
the supply current from 50mA to 100µA. The  
M27C400 is placed in the standby mode by apply-  
ing a CMOS high signal to the E input. When in the  
standby mode, the outputs are in a high imped-  
ance state, independent of the G input.  
When the BYTEV pin is at V the Byte-wide or-  
PP  
IL  
ganisation is selected and the Q15A–1 pin is used  
for the Address Input A–1. When the memory is  
2/14  

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