M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
M2060 Series
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
NBW
LOL
MUX
Phase
Detector
SAW Delay Line
RIN
RIN
DIF_REF0
nDIF_REF0
Phase
Locked
Loop
(PLL)
0
Rfec
Div
DIF_REF1
nDIF_REF1
Loop Filter
Amplifier
Phase
Shifter
1
VCSO
Mfin Divider
1,4,8,32 Options
Mfec Div
REF_SEL
Mfec/Rfec Divider
FEC_SEL1:0
FOUT0
LUT
nFOUT0
P Divider
1,4,8,32
Options
TriState
Mfin Divider
LUT
FOUT1
nFOUT1
FIN_SEL1:0
P_SEL2:0
P Divider
LUT
Figure 3: Detailed Block Diagram
Mfec and Rfec Divider Look-Up Tables (LUTs)
DIVIDER SELECTION TABLES
The FEC_SEL pins select the Mfec/Rfec divider ratio. The
look-up tables vary by device variant. The Mfec and
Rfec values also establish phase detector frequency.
A lower phase detector frequency improves jitter
tolerance and lowers loop bandwidth.
Mfin Divider Look-Up Tables (LUT)
The FIN_SEL1:0 pins select the feedback divider value
(“Mfin”), which sets the overall PLL ratio range. Since
the VCSO frequency is fixed, this allows input reference
selection. The look-up tables vary by device variant.
M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
Fvcso =
FEC_SEL1:0
0
Base Input
Mfec Rfec
Base Output
Rate (MHz)
Description
M2060/61/62: Mfin Value LUT (Includes Divide by 32)
Rate (MHz)
1
Mfin
Sample Input Reference Freq. (MHz) Options
FIN_SEL1:0
1
2
For M2060 or M2065 with Fvcso = 666.5143 (OTU1 FEC rate):
255/238 OC-48 to OTU1 encode
For M2060 , M2061 & M2062
Value
0
0
0
1
15 14
15 15
622.08 666.5143
666.5143 666.5143
0 0
0 1
1 0
1 1
32
8
4
1
19.44
77.76
155.52
622.08
OTU1 repeater or jitter attenuator
For M2060 or M2065 with Fvcso = 669.3266 (OTU2 FEC rate):
255/237 OC-192 to OTU2 encode
1
1
0
1
85 79
85 85
622.08 669.3266
669.3266 669.3266
Table 3: M2060/61/62: Mfin Value LUT (Includes Divide by 32)
OTU2 repeater or jitter attenuator
Note 1: For M2060 with Fvcso = 666.5143 or 669.3266
Note 2: For M2061 and M2062 with Fvcso = 622.0800.
Table 5: M2060/65: FEC Map LUT, OTU1 (255/238) and OTU2 (255/237)
M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
Use this option for either OTU1 or OTU2 de-mapping
applications, but not both.
M2065/66/67: Mfin Value LUT (Includes Divide by 16)
Mfin
Sample Input Reference Freq. (MHz) Options
FIN_SEL1:0
1
2
For M2065 , M2066 & M2067
Value
0 0
0 1
1 0
1 1
16
8
4
1
38.88
77.76
155.52
622.08
Fvcso =
FEC_SEL1:0
0
Base Input
Mfec Rfec
Base Output
Rate (MHz)
Description
Rate (MHz)
1
For M2061 or M2066 with Fvcso = 622.08 (OTU1 or OTU2 FEC rate):
237/255 OTU2 to OC-192 decode
0
0
1
1
0
1
0
1
79 85
79 79
14 15
14 14
669.3266 622.08
Table 4: M2065/66/67: Mfin Value LUT (Includes Divide by 16)
Note 1: For M2065 with Fvcso = 666.5143 or 669.3266
Note 2: For M2066 and M2067 with Fvcso = 622.0800.
OC-192 repeater or jitter attenuator
238/255 OTU1 to OC-48 decode
OC-48 repeater or jitter attenuator
622.08
666.5143 622.08
622.08
622.08
622.08
Table 6: M2061/66: FEC De-map LUT, OTU1 (238/255) or OTU2 (237/255)
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
3 of 12
Revised 30Jul2004
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