M2060/61/62, M2065/66/67
Integrated
Circuit
Systems, Inc.
VCSO FEC PLL FOR SONET/OTN
P r e l i m i n a r y I n f o r m a t i o n
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
Name
GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 8.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output No internal terminator
Output No internal terminator
Clock output pair 1. Differential LVPECL.
15
16
FOUT0
nFOUT0
Clock output pair 0. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 8,
P Divider Look-Up Table (LUT), on pg. 4.
1
Input
Input
Input
Input
Internal pull-down resistor
2
20
21
nDIF_REF1
DIF_REF1
Biased to Vcc/2
Reference clock input pair 1. Differential LVPECL or LVDS.
1 Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
Internal pull-down resistor
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
1
22
REF_SEL
2
23
24
nDIF_REF0
DIF_REF0
Biased to Vcc/2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
1
Internal pull-down resistor
Internal pull-down resistor
27
28
FIN_SEL1
FIN_SEL0
Input clock frequency selection. LVCMOS/LVTTL. See
Tables 3 and 4 Mfin Divider Look-Up Tables (LUT) on pg. 3.
1
Input
Input
29
30
FEC_SEL0
FEC_SEL1
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
See Tables 5, 6, and 7 on pg. 3.
1
Internal pull-down resistor
Loss of Lock indicator output. Asserted when internal PLL is
3
not tracking the input reference for frequency and phase.
Logic 1 indicates loss of lock.
31
LOL
Output
Input
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ.
Logic 0 - Wide bandwidth, RIN = 100kΩ.
Internal nodes. Connection to these pins can cause erratic
device operation.
1
32
NBW
DNC
Internal pull-UP resistor
34, 35, 36
Do Not Connect.
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 10.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 10.
Note 3: See LVCMOS Output in DC Characteristics on pg. 10.
M2060/61/62 M2065/66/67 Datasheet Rev 0.4
2 of 12
Revised 30Jul2004
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