Datasheet > M1033-11-167.7097LF

M1033-11-167.7097LF

更新时间： 2024-02-03 05:16:51

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
14页	200K
描述
PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36

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P r e l i m i n a r y I n f o r m a t i o n

Integrated

Circuit

Systems, Inc.

M1033/34

VCSO BASED CLOCK PLL WITH AUTOSWITCH

GENERAL DESCRIPTION

The M1033/34 is a VCSO (Voltage Controlled SAW

Oscillator) based clock jitter

PIN ASSIGNMENT (9 x 9 mm SMT)

attenuator PLL designed for clock

jitter attenuation and frequency

translation. The device is ideal for

generating the transmit reference

clock for optical network systems

supporting up to 2.5Gb data rates.

It can serve to jitter attenuate a

MR_SEL2

MR_SEL0

MR_SEL1

LOR

P_SEL0

P_SEL1

nFOUT

FOUT

M1033

M1034

NBW

VCC

GND

stratum reference clock or a recovered clock in loop

timing mode. The M1033/34 module includes a

proprietary SAW (surface acoustic wave) delay line as

part of the VCSO. This results in a high frequency,

high-Q, low phase noise oscillator that assures low

intrinsic output jitter.

REF_ACK

AUTO

VCC

( T o p V i e w )

DNC

GND

FEATURES

◆ Integrated SAW delay line; low phase jitter of < 0.5ps

rms, typical (12kHz to 20MHz)

Figure 1: Pin Assignment

◆ Output frequencies of 62.5 to 175 MHz

(Specify VCSO output frequency at time of order)

Example I/O Clock Frequency Combinations

Using M1033-11-155.5200 or M1034-11-155.5200

◆ LVPECL clock output (CML and LVDS options available)

◆ Reference clock inputs support differential LVDS,

LVPECL, as well as single-ended LVCMOS, LVTTL

PLL Ratio

(Pin Selectable)

Output Clock

Input Reference

Clock (MHz)

◆ Loss of Reference (LOR) output pin; Narrow Bandwidth

control input (NBW pin)

(MHz)

(Pin Selectable)

(M1033)

(M1034)

(M1033) (M1034)

◆ AutoSwitch (AUTO pin) - automatic (non-revertive)

reference clock reselection upon clock failure

19.44 or 38.88

77.76

8 or 4

155.52

77.76

◆ Acknowledge pin (REF_ACK pin) indicates the actively

selected reference input

155.52

622.08

0.25

◆ Phase Build-out only upon MUX reselection option

(PBOM)

Table 1: Example I/O Clock Frequency Combinations

◆ Pin-selectable feedback and reference divider ratios

◆ Single 3.3V power supply

◆ Small 9 x 9 mm SMT (surface mount) package

SIMPLIFIED BLOCK DIAGRAM

Loop Filter

M1033/34

NBW

MUX

PLL

DIF_REF0

nDIF_REF0

Activity

Detector

Phase

Detector

R Div

DIF_REF1

nDIF_REF1

Activity

Detector

VCSO

M Divider

LOR

REF_ACK

FOUT

nFOUT

Auto

Ref Sel

P Divider

TriState

(1, 2, or TriState)

REF_SEL

AUTO

M / R Divider

LUT

MR_SEL3:0

P_SEL1:0

P Divider

LUT

Figure 2: Simplified Block Diagram

M1033/34 Preliminary Information 0.1

Revised 07Apr2005

M1033/34 VCSO Based Clock PLL with AutoSwitch

Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400

12 3 4 5 6 7...14

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与M1033-11-167.7097LF相关器件

型号	品牌	获取价格	描述	数据表
M1033-11-168.0400	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11-168.0400LF	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11-172.6423	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11-172.6423LF	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11I155.5200	ICSI	获取价格	VCSO BASED CLOCK PLL WITH AUTOSWITCH
M1033-11I155.5200LF	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11I156.2500	ICSI	获取价格	VCSO BASED CLOCK PLL WITH AUTOSWITCH
M1033-11I156.2500LF	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11I156.8324	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9
M1033-11I161.1328LF	IDT	获取价格	PLL Based Clock Driver, 1033 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9

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