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LTC2355-12_15 PDF预览

LTC2355-12_15

更新时间: 2024-02-13 03:51:30
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
18页 285K
描述
Serial 12-Bit/14-Bit, 3.5Msps Sampling ADCs with Shutdown

LTC2355-12_15 数据手册

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LTC2355-12/LTC2355-14  
Serial 12-Bit/14-Bit, 3.5Msps  
Sampling ADCs with Shutdown  
Features  
Description  
TheLTC®2355-12/LTC2355-14are12-bit/14-bit, 3.5Msps  
n
3.5Msps Conversion Rate  
n
74.2dB SINAD at 14-Bits, 71.1dB SINAD at 12-Bits  
Low Power Dissipation: 18mW  
serial ADCs with differential inputs. The devices draw  
only 5.5mA from a single 3.3V supply and come in a  
tiny 10-lead MSOP package. A Sleep shutdown feature  
further reduces power consumption to 13µW. The com-  
bination of speed, low power and tiny package makes the  
LTC2355-12/LTC2355-14suitableforhighspeed,portable  
applications.  
n
n
n
n
n
n
n
n
n
3.3V Single Supply Operation  
2.5V Internal Bandgap Reference can be Overdriven  
3-Wire SPI-Compatible Serial Interface  
Sleep (13µW) Shutdown Mode  
Nap (4mW) Shutdown Mode  
80dB Common Mode Rejection  
The80dBcommonmoderejectionallowsuserstoeliminate  
ground loops and common mode noise by measuring  
signals differentially from the source.  
0V to 2.5V Unipolar Input Range  
Tiny 10-Lead MSOP Package  
Thedevicesconvert0Vto2.5Vunipolarinputsdifferentially.  
applications  
+
TheabsolutevoltageswingforA andA extendsfrom  
IN  
IN  
ground to the supply voltage.  
n
Communications  
n
Data Acquisition Systems  
Theserialinterfacesendsouttheconversionresultsduring  
the 16 clock cycles following a CONV rising edge for com-  
patibility with standard serial interfaces. If two additional  
clock cycles for acquisition time are allowed after the data  
stream in between conversions, the full sampling rate of  
3.5Msps can be achieved with a 63MHz clock.  
n
Uninterrupted Power Supplies  
n
Multiphase Motor Control  
n
Multiplexed Data Acquisition  
n
RFID  
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear  
Technology Corporation. All other trademarks are the property of their respective owners.  
Block Diagram  
10µF 3.3V  
THD, 2nd, 3rd and SFDR  
vs Input Frequency  
–50  
7
V
LTC2355-14  
DD  
–56  
–62  
+
THREE-  
STATE  
SERIAL  
OUTPUT  
PORT  
A
A
IN  
IN  
1
2
+
THD  
–68  
2nd  
–74  
14-BIT ADC  
SDO  
S & H  
8
3rd  
–80  
14  
–86  
V
REF  
–92  
3
4
10  
9
CONV  
SCK  
–98  
2.5V  
REFERENCE  
TIMING  
LOGIC  
10µF  
GND  
5
–104  
–110  
2355 TA01  
0.1  
1
10  
100  
6
11  
EXPOSED PAD  
FREQUENCY (MHz)  
2355 G02  
2355fa  

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