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LTC2315HTS8-12#PBF

更新时间： 2024-02-09 05:43:06
品牌 Logo 应用领域
凌特 - Linear /
页数 文件大小 规格书
22页 684K
描述
LTC2315-12 - 12-Bit, 5Msps Serial Sampling ADC in TSOT; Package: SOT; Pins: 8; Temperature Range: -40°C to 125°C

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LTC2315HTS8-12#PBF 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：SOT包装说明：LEAD FREE, PLASTIC, MO-193, TSOT-23, 8 PIN
针数：8Reach Compliance Code：compliant
风险等级：5.65Base Number Matches：1

LTC2315HTS8-12#PBF 数据手册

 浏览型号LTC2315HTS8-12#PBF的Datasheet PDF文件第2页浏览型号LTC2315HTS8-12#PBF的Datasheet PDF文件第3页浏览型号LTC2315HTS8-12#PBF的Datasheet PDF文件第4页浏览型号LTC2315HTS8-12#PBF的Datasheet PDF文件第6页浏览型号LTC2315HTS8-12#PBF的Datasheet PDF文件第7页浏览型号LTC2315HTS8-12#PBF的Datasheet PDF文件第8页 
LTC2315-12  
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating  
temperature range, otherwise specifications are at TA = 25°C. (Note 4)  
SYMBOL  
PARAMETER  
CONDITIONS  
(Notes 7, 8)  
(Notes 7, 8)  
MIN  
TYP  
MAX  
5
UNITS  
MHz  
MHz  
ns  
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Maximum Sampling Frequency  
Shift Clock Frequency  
Shift Clock Period  
SAMPLE(MAX)  
87.5  
SCK  
11.4  
SCK  
Minimum Throughput Time, t  
Conversion Time  
+ t  
CONV  
200  
ns  
THROUGHPUT  
ACQ  
160  
40  
5
ns  
CONV  
Acquisition Time  
ns  
ACQ  
1
Minimum CS Pulse Width  
SCK Setup Time After CS↓  
SDO Enable Time After CS↓  
(Note 7)  
ns  
(Note 7)  
5
ns  
2
(Notes 7, 8)  
(Notes 7, 8, 9)  
10  
ns  
3
SDO Data Valid Access Time after SCK↓  
SCLK Low Time  
9.1  
ns  
4
4.5  
4.5  
1
ns  
5
SCLK High Time  
ns  
6
SDO Data Valid Hold Time After SCK↓  
SDO into Hi-Z State Time After 16th SCK↓  
SDO into Hi-Z State Time After CS↑  
CS↑ Setup Time After 14th SCK↓  
Latency  
(Notes 7, 8, 9)  
(Notes 7, 8, 10)  
(Notes 7, 8, 10)  
(Note 7)  
ns  
7
3
10  
10  
ns  
8
3
ns  
9
5
ns  
10  
1 Cycle Latency  
t
t
_
Power-Up Time from Nap Mode  
Power-Up Time from Sleep Mode  
See Nap Mode Section  
See Sleep Mode Section  
50  
ns  
WAKE NAP  
_
1.1  
ms  
WAKE SLEEP  
Note 1. Stresses beyond those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. Exposure to any Absolute  
Maximum Rating condition for extended periods may affect device  
reliability and lifetime.  
Note 6. Typical RMS noise at code transitions.  
Note 7. Parameter tested and guaranteed at OV = 2.5V. All input signals  
DD  
are specified with t = t = 1nS (10% to 90% of OV ) and timed from a  
r
f
DD  
voltage level of OV /2.  
DD  
Note 2. All voltage values are with respect to ground.  
Note 8. All timing specifications given are with a 10pF capacitance load.  
Note 3. When these pin voltages are taken below ground or above V  
Load capacitances greater than this will require a digital buffer.  
DD  
(A , REF) or OV (SCK, CS, SDO) they will be clamped by internal  
IN  
DD  
Note 9. The time required for the output to cross the V or V voltage.  
Note 10. Guaranteed by design, not subject to test.  
Note 11. Recommended operating conditions.  
IH  
IL  
diodes. This product can handle input currents up to 100mA below ground  
or above V or OV without latch-up.  
DD  
DD  
Note 4. V = 5V, OV = 2.5V, f  
= 5MHz, f = 87.5MHz, A =  
SCK IN  
DD  
DD  
SMPL  
–1dBFS and internal reference unless otherwise noted.  
Note 5. Integral nonlinearity is defined as the deviation of a code from a  
straight line passing through the actual endpoints of the transfer curve.  
The deviation is measured from the center of the quantization band.  
231512fa  
5
For more information www.linear.com/LTC2315-12  
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