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LTC1664

更新时间： 2023-12-20 18:46:08
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
16页 228K
描述
微功率、四通道 10 位 DAC

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中文翻译

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LTC1664 数据手册

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LTC1664  
operation  
Transfer Function  
Multiple LTC1664’s can be controlled from a single 3-wire  
serialport(i.e., SCK, D andCS/LD)byusingtheincluded  
IN  
The transfer function is  
daisychain facility. A series of m chips is configured by  
k
connecting each D  
(except the last) to D of the next  
OUT  
IN  
VOUT(IDEAL)  
=
V
REF  
1024  
chip, forming a single 16m-bit shift register. The SCK and  
CS/LD signals are common to all chips in the chain. In  
use, CS/LD is held low while m 16-bit words are clocked  
where k is the decimal equivalent of the binary DAC input  
code and V is the voltage at REF (Pin 6).  
REF  
to D of the first chip; CS/LD is then pulled high, updating  
IN  
all of them simultaneously.  
Power-On Reset  
The LTC1664 clears the outputs to zero-scale when power  
is first applied, making system initialization consistent  
and repeatable.  
Sleep Mode  
DACaddress1110 isreservedforthespecialsleepinstruc-  
b
tion (see Table 2). In this mode, the digital interface stays  
active while the analog circuits are disabled; static power  
consumption is thus virtually eliminated. The reference  
input and analog outputs are set in a high impedance state  
and all DAC settings are retained in memory so that when  
sleep mode is exited, the outputs of DACs not updated by  
the Wake command are restored to their last active state.  
Power Supply Sequencing  
The voltage at REF (Pin 6) should be kept within the range  
–0.3V ≤ V ≤ V + 0.3V (see Absolute Maximum Rat-  
REF  
CC  
ings). Particular care should be taken to observe these  
limitsduringpowersupplyturn-onandturn-offsequences,  
when the voltage at V (Pin 16) is in transition. If it is  
CC  
Sleep mode is initiated by performing a load sequence to  
not possible to sequence the supplies, connect a Schottky  
address 1110 (the DAC input word D9-D0 is ignored).  
diode from REF (anode) to V (cathode).  
b
CC  
Once in sleep mode, a load sequence to any other ad-  
Serial Interface  
dress (including “No Change” address 0000 ) causes  
b
the LTC1664 to Wake. It is possible to keep one or more  
chips of a daisy chain in continuous sleep mode by giving  
the sleep instruction to these chips each time the active  
chips in the chain are updated.  
Referring to Figure 2: With CS/LD held low, data on the D  
IN  
input is shifted into the 16-bit shift register on the positive  
edge of SCK. The 4-bit DAC address, A3-A0, is loaded first  
(see Table 2), then the 10-bit input code, D9-D0, ordered  
MSꢀ-to-LSꢀ in each case. Two don’t-care bits, X1-X0,  
are loaded last. When the full 16-bit input word has been  
shifted in, CS/LD is pulled high, loading the DAC register  
with the word and causing the addressed DAC output(s)  
to update. The clock is disabled internally when CS/LD is  
high. Note: SCK must be low before CS/LD is pulled low.  
Voltage Outputs  
Each of the four rail-to-rail output amplifiers contained in  
the LTC1664 can source or sink up to 5mA. The outputs  
swing to within a few millivolts of either supply rail when  
unloadedandhaveanequivalentoutputresistanceof85Ω  
when driving a load to the rails. The output amplifiers are  
stable driving capacitive loads of up to 1000pF.  
The buffered serial output of the shift register is avail-  
able on the D  
pin, which swings from GND to V .  
OUT  
OUT  
CC  
A small resistor placed in series with the output can be  
used to achieve stability for any load capacitance. A 1µF  
Data appears on D  
16 positive SCK edges after being  
applied to D .  
IN  
Table 1. LTC1664 Input Word  
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0  
ADDRESS/CONTROL INPUT CODE DON’T CARE  
1664fa  
8
1...567891011...16

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