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LTC1412 PDF预览

LTC1412

更新时间： 2023-12-20 18:44:05
品牌 Logo 应用领域
亚德诺 - ADI 转换器
页数 文件大小 规格书
16页 338K
描述
12 位、3Msps、采样 A/D 转换器

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中文翻译

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LTC1412 数据手册

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LTC1412  
W U  
(Note 5)  
TI I G CHARACTERISTICS  
SYMBOL  
PARAMETER  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
MHz  
ns  
f
t
t
t
t
t
t
Maximum Sampling Frequency  
Throughput Time (Acquisition + Conversion)  
Conversion Time  
●
●
●
●
●
●
3
SAMPLE(MAX)  
333  
283  
50  
THROUGHPUT  
240  
20  
ns  
CONV  
Acquisition Time  
ns  
ACQ  
CS↓ to CONVST↓ Setup Time  
CONVST Low Time  
(Notes 9, 10)  
(Note 10)  
5
ns  
1
2
3
20  
ns  
CONVST to BUSY Delay  
C = 25pF  
L
5
0
ns  
ns  
●
20  
t
Data Ready Before BUSY↑  
–20  
–25  
20  
25  
ns  
ns  
4
●
●
t
t
Delay Between Conversions  
(Note 10)  
50  
ns  
5
6
Data Access Time After CS↓  
C = 25pF  
L
10  
8
35  
45  
ns  
ns  
●
t
Bus Relinquish Time  
30  
35  
40  
ns  
ns  
ns  
7
LTC1412C  
LTC1412I  
●
●
t
t
CONVST High Time  
●
20  
ns  
ns  
8
9
Aperture Delay of Sample-and-Hold  
–1  
The  
● denotes specifications which apply over the full operating  
Note 5: V = 5V, f  
specified.  
= 3MHz and t = t = 5ns unless otherwise  
r f  
DD  
SAMPLE  
temperature range; all other limits and typicals T = 25°C.  
A
Note 1: Absolute Maximum Ratings are those values beyond which the life  
of a device may be impaired.  
Note 6: Linearity, offset and full-scale specifications apply for a single-  
–
ended A input with A grounded.  
IN  
IN  
Note 2: All voltage values are with respect to ground with DGND and  
AGND wired together (unless otherwise noted).  
Note 7: Integral nonlinearity is defined as the deviation of a code from a  
straight line passing through the actual endpoints of the transfer curve.  
The deviation is measured from the center of the quantization band.  
Note 3: When these pin voltages are taken below V or above V , they  
SS  
DD  
will be clamped by internal diodes. This product can handle input currents  
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB  
when the output code flickers between 0000 0000 0000 and  
1111 1111 1111.  
greater than 100mA below V or above V without latchup.  
SS  
DD  
Note 4: When these pin voltages are taken below V they will be clamped  
SS  
by internal diodes. This product can handle input currents greater than  
Note 9: Guaranteed by design, not subject to test.  
Note 10: Recommended operating conditions.  
100mA below V without latchup. These pins are not clamped to V  
.
SS  
DD  
W U  
W
TI I G DIAGRA  
CS  
t
CONV  
t
1
t
2
CONVST  
BUSY  
t
t
5
3
t
t
t
7
6
4
DATA (N – 1)  
DB11 TO DB0  
DATA N  
DB11 TO DB0  
DATA (N + 1)  
DB11 TO DB0  
DATA  
1412 TD  
4
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