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LTC1264-7CSW PDF预览

LTC1264-7CSW

更新时间: 2024-01-24 20:18:05
品牌 Logo 应用领域
凌特 - Linear 有源滤波器过滤器光电二极管LTE
页数 文件大小 规格书
16页 295K
描述
Linear Phase, Group Delay Equalized, 8th Order Lowpass Filter

LTC1264-7CSW 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, SO-14
针数:14Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.68有源滤波器类型:SWITCHED CAPACITOR FILTER
中心频率或截止频率最大范围:250 kHz中心频率或截止频率最小范围:
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm功能数量:1
端子数量:14封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极和零点:8 AND 0
认证状态:Not Qualified响应:LOWPASS
座面最大高度:1.75 mm表面贴装:YES
技术:CMOS端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL传递特性:BESSEL
宽度:3.9 mmBase Number Matches:1

LTC1264-7CSW 数据手册

 浏览型号LTC1264-7CSW的Datasheet PDF文件第8页浏览型号LTC1264-7CSW的Datasheet PDF文件第9页浏览型号LTC1264-7CSW的Datasheet PDF文件第10页浏览型号LTC1264-7CSW的Datasheet PDF文件第12页浏览型号LTC1264-7CSW的Datasheet PDF文件第13页浏览型号LTC1264-7CSW的Datasheet PDF文件第14页 
LTC1264-7  
U
U
U
PI FU CTIO S  
External Connection Pins (7, 14)  
Clock Input Pin (11)  
Pins 7 and 14 should be connected together. In a printed  
circuit board the connection should be done under the IC  
package through a short trace surrounded by the analog  
ground plane.  
Any TTL or CMOS clock source with a square-wave output  
and 50% duty cycle (±10%) is an adequate clock source  
for the device. The power supply for the clock source  
should not be the filter’s power supply. The analog ground  
for the filter should be connected to clock’s ground at a  
single point only. Table 7 shows the clock’s low and high  
levelthresholdvaluesforadualorsinglesupplyoperation.  
A pulse generator can be used as a clock source provided  
thehighlevelONtimeisgreaterthan0.1µs. Sinewavesare  
not recommended for clock input frequencies less than  
100kHz, since excessively slow clock rise or fall times  
generate internal clock jitter (maximum clock rise or fall  
time 1µs). The clock signal should be routed from the  
right side of the IC package and perpendicular to it to avoid  
coupling to any input or output analog signal path. A 200Ω  
resistor between clock source and pin 11 will slow down  
the rise and fall times of the clock to further reduce charge  
coupling (Figures 2 and 3).  
Ratio Input Pin (10)  
The DC level at this pin determines the ratio of the clock  
frequency to the cutoff frequency of the filter. Pin 10 at V+  
gives a 25:1 ratio and pin 10 at Vgives a 50:1 ratio. For  
single supply operation the ratio is 25:1 when pin 10 is at  
V+ and 50:1 when pin 10 is at ground. When pin 10 is not  
tied to ground, it should be bypassed to analog ground  
with a 0.1µF capacitor. If the DC level at pin 10 is switched  
mechanically or electrically at slew rates greater than  
1V/µs while the device is operating, a 10k resistor should  
be connected between pin 10 and the DC source.  
Table 7. Clock Source High and Low Threshold Levels  
POWER SUPPLY  
HIGH LEVEL  
LOW LEVEL  
Dual Supply = ±7.5V  
Dual Supply = ±5V  
Dual Supply = ± 2.5V  
Single Supply = 12V  
Single Supply = 5V  
2.18V  
1.45V  
0.73V  
7.80V  
1.45V  
0.5V  
0.5V  
– 2.0V  
6.5V  
0.5V  
12647fa  
11  

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