Datasheet > LTC1257

LTC1257

更新时间： 2023-12-20 18:45:17

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
12页	201K
描述
采用 SO-8 封装的完整单电源 12 位电压输出 DAC

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数据手册

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LTC1257 数据手册

LTC1257

PIN FUNCTIONS

(Pin 8): The positive supply input. 4.75V ≤ V

≤

(Pin 7): The buffered DAC output is capable of

OUT

15.75V. Requires a bypass capacitor to ground.

sourcing 2mA over temperature while pulling within 2.7V

of V . The output will pull to ground through an internal

250Ω equivalent resistance.

DEFINITIONS

LSB:Theleastsignificantbitortheidealvoltagedifference

between two successive codes.

OUTPUT

VOLTAGE

LSB = (V – V )/2 – 1

= The number of digital input bits

NEGATIVE

OFFSET

DAC CODE

= The zero code error or offset of the DAC

= The full-scale output voltage of the DAC

measured when all bits are set to 1

{

1257 F01

Figure 1. Effect of Negative Offset

Resolution: The resolution is the number of DAC output

The offset of the part is measured at the first code that

produces an output voltage 0.5LSB greater than the

previous code:

states (2 ) that divide the full-scale range. The resolution

does not imply linearity.

INL:End-pointintegralnonlinearityisthemaximumdevia-

tion from a straight line passing through the end-points of

the DAC transfer curve. Because the part operates from

a single supply and the output cannot go below ground,

the linearity is measured between full-scale and the first

code that guarantees a positive output. The INL error at

a given input code is calculated as follows:

= V

– [(Code)(V )/(2 – 1)]

OUT

Full-ScaleError:Full-scaleerroristhedifferencebetween

the ideal and measured DAC output voltages with all bits

set to one (Code = 4095). The full-scale error includes the

offset error and is calculated as follows:

FSE = (V

– V

)/LSB

REF OS

=Thereferencevoltage,eitherinternalorexternal

OUT

IDEAL

–n

= (V )(1 – 2 ) – V

INL = (V

– V

)/LSB

IDEAL

REF

OUT

IDEAL

OUT

= (Code)(LSB) + V

= The output voltage of the DAC measured at

the given input code

Gain Error: Gain error is the difference between the ideal

and measured slope of the DAC transfer characteristic.

Gain error is equal to full-scale error minus offset error.

DNL: Differential nonlinearity is the difference between

the measured change and the ideal 1LSB change between

any two adjacent codes. The DNL error between any two

codes is calculated as follows:

Digital Feedthrough: The glitch that appears at the analog

outputcausedbyACcouplingfromthedigitalinputswhen

they change state. The area of the glitch is specified in

(nV)(sec).

DNL = (∆V

– LSB)/LSB

OUT

∆V

= The measured voltage difference between two

OUT

adjacent codes

Offset Error: The theoretical voltage at the output when

the DAC is loaded with all zeros. The output amplifier can

have a true negative offset, but because the part is oper-

ated from a single supply, the output cannot go below

ground. If the offset is negative, the output will remain

near 0V resulting in the transfer curve shown in Figure 1.

1257fc

1...3 4 567 8 9...12

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与LTC1257相关器件

型号	品牌	获取价格	描述	数据表
LTC1257_01	Linear	获取价格	Complete Single Supply 12-Bit Voltage Output DAC in SO-8
LTC1257C	Linear	获取价格	Complete Single Supply 12-Bit Voltage Output DAC in SO-8
LTC1257CN8	Linear	获取价格	Complete Single Supply 12-Bit Voltage Output DAC in SO-8
LTC1257CN8#PBF	Linear	获取价格	LTC1257 - Complete Single Supply 12-Bit Voltage Output DAC in SO-8; Package: PDIP; Pins: 8
LTC1257CN8#TRPBF	Linear	获取价格	IC 12-BIT DAC, Digital to Analog Converter
LTC1257CS8	Linear	获取价格	Complete Single Supply 12-Bit Voltage Output DAC in SO-8
LTC1257CS8#PBF	Linear	获取价格	LTC1257 - Complete Single Supply 12-Bit Voltage Output DAC in SO-8; Package: SO; Pins: 8;
LTC1257CS8#TR	Linear	获取价格	LTC1257 - Complete Single Supply 12-Bit Voltage Output DAC in SO-8; Package: SO; Pins: 8;
LTC1257CS8#TRPBF	Linear	获取价格	LTC1257 - Complete Single Supply 12-Bit Voltage Output DAC in SO-8; Package: SO; Pins: 8;
LTC1257I	Linear	获取价格	Complete Single Supply 12-Bit Voltage Output DAC in SO-8

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