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LTC1069-1CS8#TR PDF预览

LTC1069-1CS8#TR

更新时间： 2024-02-04 06:00:27
品牌 Logo 应用领域
凌特 - Linear LTE光电二极管有源滤波器
页数 文件大小 规格书
10页 137K
描述
LTC1069-1 - Low Power, 8th Order Progressive Elliptic, Lowpass Filter; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C

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LTC1069-1CS8#TR 技术参数

是否Rohs认证： 不符合生命周期：Transferred
零件包装代码：SOIC包装说明：SOP,
针数：8Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.25有源滤波器类型：SWITCHED CAPACITOR FILTER
中心频率或截止频率最大范围：8 kHz中心频率或截止频率最小范围：
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.9 mm湿度敏感等级：1
负电源电压最大值（Vsup）：-5.5 V负电源电压最小值（Vsup）：-1.57 V
标称负供电电压 (Vsup)：-5 V功能数量：1
端子数量：8最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：235
极和零点：8 AND 0认证状态：Not Qualified
响应：LOWPASS座面最大高度：1.75 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.57 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：20传递特性：ELLIPTIC
宽度：3.9 mm

LTC1069-1CS8#TR 数据手册

 浏览型号LTC1069-1CS8#TR的Datasheet PDF文件第3页浏览型号LTC1069-1CS8#TR的Datasheet PDF文件第4页浏览型号LTC1069-1CS8#TR的Datasheet PDF文件第5页浏览型号LTC1069-1CS8#TR的Datasheet PDF文件第7页浏览型号LTC1069-1CS8#TR的Datasheet PDF文件第8页浏览型号LTC1069-1CS8#TR的Datasheet PDF文件第9页 
LTC1069-1  
PIN FUNCTIONS  
AGND (Pin 1): Analog Ground. The quality of the analog  
signal ground can affect the filter performance. For either  
single or dual supply operation, an analog ground plane  
surrounding the package is recommended. The analog  
ground plane should be connected to any digital ground  
at a single point. For dual supply operation Pin 1 should  
be connected to the analog ground plane.  
CLK(Pin5):ClockInputPin.AnyTTLorCMOSclocksource  
with a square wave output and 50% duty cycle ( 10%) is  
an adequate clock source for the device. The power supply  
for the clock source should not necessarily be the filter’s  
power supply. The analog ground of the filter should be  
connected to clock’s ground at a single point only. Table 1  
shows the clock’s low and high level threshold value for a  
dual or a single supply operation. A pulse generator can be  
used as a clock source provided the high level ON time is  
For single supply operation Pin 1 should be bypassed to  
the analog ground plane with a 0.47μF or larger capaci-  
tor. An internal resistive divider biases Pin 1 to 1/2 the  
total power supply. Pin 1 should be buffered if used to  
bias other ICs. Figure 1 shows the connections for single  
supply operation.  
greaterthan0.42μs(V = 5V).Sinewaveslessthan100kHz  
S
are not recommended for clock signal because excessive  
slow clock rise or fall times generate internal clock jitter.  
The maximum clock rise or fall is 1μs. The clock signal  
should be routed from the right side of the IC package to  
avoid coupling into any input or output analog signal path.  
A 1k resistor between the clock source and the clock input  
pin (5) will slow down the rise and fall times of the clock  
to further reduce charge coupling, Figure 1.  
+
–
+
V , V (Pins 2, 7): Power Supply Pins. The V (Pin 2) and  
–
the V (Pin 7) should be bypassed with a 0.1μF capacitor  
to an adequate analog ground. The filter’s power supplies  
shouldbeisolatedfromotherdigitalorhighvoltageanalog  
supplies.Alownoiselinearsupplyisrecommended.Using  
switching power supplies will lower the signal-to-noise  
ratio of the filter. Unlike previous monolithic filters, the  
power supplies can be applied at any order, that is, the  
positive supply can be applied before the negative supply  
and vice versa. Figure 2 shows the connection for dual  
supply operation.  
Table 1. Clock Source High and Low Thresholds  
POWER SUPPLY  
HIGH LEVEL  
1.5V  
LOW LEVEL  
0.5V  
Dual Supply = 5V  
Single Supply = 10V  
Single Supply = 5V  
Single Supply = 3.3V  
6.5V  
5.5V  
1.5V  
0.5V  
1.2V  
0.5V  
NC (Pins 3, 6): No Connection. Pins 3 and 6 are not con-  
nected to any internal circuity; they should be preferably  
tied to ground.  
V
(Pin 8): Filter Output Pin. Pin 8 is the output of the  
OUT  
filter and it can source or sink 1mA. Driving coaxial cables  
or resistive loads less than 20k will degrade the total har-  
monic distortion of the filter. When evaluating the device’s  
dynamic range, a buffer is required to isolate the filter’s  
output from coax cables and instruments.  
V (Pin 4): Filter Input Pin. The filter input pin is internally  
IN  
connected to the inverting input of an op amp through a  
43k resistor.  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
AGND  
V
V
AGND  
V
V
OUT  
OUT  
OUT  
OUT  
0.47μF  
V
0.1μF  
+
+
–
+
+
–
–
V
V
V
V
V
V
LTC1069-1  
LTC1069-1  
0.1μF  
0.1μF  
NC  
NC  
NC  
NC  
V
IN  
V
IN  
V
CLK  
V
IN  
CLK  
IN  
ANALOG GROUND PLANE  
ANALOG GROUND PLANE  
STAR  
SYSTEM  
GROUND  
DIGITAL  
GROUND  
PLANE  
STAR  
SYSTEM  
GROUND  
DIGITAL  
GROUND  
PLANE  
1k  
1k  
CLOCK  
SOURCE  
CLOCK  
SOURCE  
10691 F01  
10691 F02  
Figure 1. Connections for Single Supply Operation  
Figure 2. Connections for Dual Supply Operation  
10691fa  
6
1...345678910

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