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LMX2305TMX PDF预览

LMX2305TMX

更新时间： 2024-02-12 22:54:33
品牌 Logo 应用领域
罗彻斯特 - ROCHESTER 信息通信管理光电二极管
页数 文件大小 规格书
15页 435K
描述
PLL Frequency Synthesizer, BICMOS, PDSO20, 0.173 INCH, PLASTIC, TSSOP-20

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LMX2305TMX 技术参数

生命周期：Obsolete包装说明：,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.7模拟集成电路 - 其他类型：PLL FREQUENCY SYNTHESIZER
Base Number Matches：1

LMX2305TMX 数据手册

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Connection Diagram  
LMX2305  
TL/W/12459–2  
20-Lead (0.173 Wide) Thin Shrink  
×
Small Outline Package (TM)  
Order Number LMX2305TM or LMX2305TMX  
See NS Package Number MTC20  
Pin Descriptions  
Pin No.  
Pin Name  
I/O  
Description  
1
OSC  
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal resonator for  
operation as an oscillator. The input has a V /2 input threshold and can be driven from an  
IN  
CC  
external CMOS or TTL logic gate. May also be from a reference oscillator.  
Oscillator output.  
3
4
5
OSC  
O
OUT  
t
V
V
Power supply for charge pump. Must be  
V
CC  
.
P
Power supply voltage input. Input may range from 2.65V to 5.5V. Bypass capacitors should be  
placed as close as possible to this pin and be connected directly to the ground plane.  
CC  
6
D
O
O
Internal charge pump output. For connection to a loop filter for driving the input of an external  
VCO.  
o
7
8
GND  
LD  
Ground.  
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’. When the loop is  
locked, the pin’s output is HIGH with narrow low pulses.  
10  
11  
f
I
I
Prescaler input. Small signal input from the VCO.  
IN  
CLOCK  
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the various  
counters and registers.  
13  
14  
DATA  
LE  
I
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance CMOS input.  
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data stored in the  
shift registers is loaded into the appropriate latch (control bit dependent). Clock must be low  
when LE toggles high or low. See Serial Data Input Timing Diagram.  
15  
16  
FC  
I
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of the phase  
comparator and charge pump combination is reversed.  
BISW  
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the internal charge  
pump output through BISW (as well as through D ).  
o
17  
18  
f
O
O
Monitor pin of phase comparator input. CMOS output.  
OUT  
w
Output for external charge pump. w is an open drain N-channel transistor and requires a pull-up  
p
p
resistor.  
19  
PWDN  
I
Power Down (with internal pull-up resistor).  
e
e
PWDN  
PWDN  
HIGH for normal operation.  
LOW for power saving.  
Power down function is gated by the return of the charge pump to a TRI-STATE condition.  
20  
w
O
Output for external charge pump. w is a CMOS logic output.  
r
r
2,9,12  
NC  
No connect.  
http://www.national.com  
2
1234567...15

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