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LM810M3-2.93/NOPB PDF预览

LM810M3-2.93/NOPB

更新时间: 2023-07-15 00:00:00
品牌 Logo 应用领域
美国国家半导体 - NSC 光电二极管
页数 文件大小 规格书
9页 214K
描述
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO3, SOT-23, 3 PIN

LM810M3-2.93/NOPB 数据手册

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Typically, for the 4.63V and 4.38V version of the LM809/810,  
a VCC transient that goes 100mV below the reset threshold  
and lasts 20µs or less will not cause a reset pulse. A 0.1 µF  
bypass capacitor mounted as close as possible to the VCC  
pin will provide additional transient rejection.  
Applications Information  
Benefits of Precision Reset Thresholds  
A microprocessor supply supervisor must provide a reset  
output within a predictable range of the supply voltage. A  
common threshold range is between 5% and 10% below the  
nominal supply voltage. The 4.63V and 3.08V options of the  
LM809/810 use highly accurate circuitry to ensure that the  
reset threshold occurs only within this range (for 5V and 3.3V  
supplies). The other voltage options have the same tight  
tolerance to ensure a reset signal for other narrow monitor  
ranges. See Table 1 for examples of how the standard reset  
thresholds apply to 3V, 3.3V, and 5V nominal supply volt-  
ages.  
TABLE 1. Reset Thresholds Related to Common  
Supply Voltages  
Reset  
3.0V  
3.3V  
5.0V  
Threshold  
4.63 3%  
4.38 3%  
4.00 3%  
3.08 3%  
2.93 3%  
2.63 3%  
2.45 3%  
90 - 95%  
85 - 90%  
78 - 82%  
10105709  
FIGURE 2. Maximum Transient Duration without  
Causing a Reset Pulse vs. Reset Comparator  
Overdrive  
90 - 95%  
86 - 90%  
77 - 81%  
72 - 76%  
85 - 90%  
79 - 84%  
Interfacing to µPs with Bidirectional Reset Pins  
Microprocessors with bidirectional reset pins, such as the  
Motorola 68HC11 series, can be connected to the LM809  
RESET output. To ensure a correct output on the LM809  
even when the microprocessor reset pin is in the opposite  
state, connect a 4.7kresistor between the LM809 RESET  
output and the µP reset pin, as shown in Figure 3. Buffer the  
LM809 RESET output to other system components.  
Ensuring a Valid Reset Output Down to VCC = 0V  
When VCC falls below 1V, the LM809 RESET output no  
longer sinks current. A high-impedance CMOS logic input  
connected to RESET can therefore drift to undetermined  
voltages. To prevent this situation, a 100kresistor should  
be connected from the RESET output to ground, as shown in  
Figure 1.  
A 100kpull-up resistor to VCC is also recommended for the  
<
LM810, if RESET is required to remain valid for VCC 1V.  
10105711  
10105710  
FIGURE 3. Interfacing to Microprocessors with  
Bidirectional Reset I/O  
FIGURE 1. RESET Valid to VCC = Ground Circuit  
Negative-Going VCC Transients  
LLP Mounting  
The LM809/810 are relatively immune to short  
negative-going transients or glitches on VCC. Figure 2 shows  
the maximum pulse width a negative-going VCC transient  
can have without causing a reset pulse. In general, as the  
magnitude of the transient increases, going further below the  
threshold, the maximum allowable pulse width decreases.  
The LLP package requires special mounting techniques  
which are detailed in National Semiconductor Application  
Note AN-1187. Referring to the section PCB Design Recom-  
mendations, it should be noted that the pad style which  
should be used with the LLP package is the NSMD (non-  
solder mask defined) type.  
www.national.com  
6

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