Datasheet > LM555MDC

LM555MDC

更新时间： 2024-02-06 15:53:33

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
12页	400K
描述
IC,TIMER,BIPOLAR,DIE

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技术参数
数据手册

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LM555MDC 技术参数

生命周期：	Obsolete	包装说明：	, DIE OR CHIP
Reach Compliance Code：	unknown	风险等级：	5.84
最高工作温度：	70 °C	最低工作温度：
封装等效代码：	DIE OR CHIP	电源：	5/15 V
认证状态：	Not Qualified	子类别：	Analog Waveform Generation Functions
技术：	BIPOLAR	温度等级：	COMMERCIAL

LM555MDC 数据手册

Applications Information

MONOSTABLE OPERATION

NOTE: In monostable operation, the trigger should be driven

high before the end of timing cycle.

In this mode of operation, the timer functions as a one-shot

(Figure 1). The external capacitor is initially held discharged

by a transistor inside the timer. Upon application of a nega-

tive trigger pulse of less than 1/3 V_CCto pin 2, the flip-flop is

set which both releases the short circuit across the capacitor

and drives the output high.

DS007851-7

FIGURE 3. Time Delay

ASTABLE OPERATION

If the circuit is connected as shown in Figure 4 (pins 2 and 6

connected) it will trigger itself and free run as a multivibrator.

The external capacitor charges through R_A+ R_Band dis-

charges through R_B. Thus the duty cycle may be precisely

set by the ratio of these two resistors.

DS007851-5

FIGURE 1. Monostable

The voltage across the capacitor then increases exponen-

tially for a period of t = 1.1 R_AC, at the end of which time the

voltage equals 2/3 V_CC. The comparator then resets the

flip-flop which in turn discharges the capacitor and drives the

output to its low state. Figure 2 shows the waveforms gener-

ated in this mode of operation. Since the charge and the

threshold level of the comparator are both directly propor-

tional to supply voltage, the timing internal is independent of

supply.

DS007851-8

FIGURE 4. Astable

DS007851-6

In this mode of operation, the capacitor charges and dis-

charges between 1/3 V_CCand 2/3 V_CC. As in the triggered

mode, the charge and discharge times, and therefore the fre-

quency are independent of the supply voltage.

= 5V

Top Trace: Input 5V/Div.

TIME = 0.1 ms/DIV.

= 9.1kΩ

Middle Trace: Output 5V/Div.

Bottom Trace: Capacitor Voltage 2V/Div.

C = 0.01µF

FIGURE 2. Monostable Waveforms

During the timing cycle when the output is high, the further

application of a trigger pulse will not effect the circuit so long

as the trigger input is returned high at least 10µs before the

end of the timing interval. However the circuit can be reset

during this time by the application of a negative pulse to the

reset terminal (pin 4). The output will then remain in the low

state until a trigger pulse is again applied.

When the reset function is not in use, it is recommended that

it be connected to V_CCto avoid any possibility of false trig-

gering.

Figure 3 is a nomograph for easy determination of R, C val-

ues for various time delays.

www.national.com

1...4 5 678 9 10...12

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