Datasheet > LH7A400N0E000B5

LH7A400N0E000B5

更新时间： 2024-02-02 16:48:35

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
65页	814K
描述
32-Bit System-on-Chip

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技术参数
数据手册

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LH7A400N0E000B5 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Sampling Now	Reach Compliance Code：	unknown
风险等级：	5.73	Base Number Matches：	1

LH7A400N0E000B5 数据手册

32-Bit System-on-Chip

NXP Semiconductors

LH7A400

Table 3. Functional Pin List (Cont’d)

BGA LFBGA

SIGNAL

RESET

STATE

STANDBY

STATE

OUTPUT

DRIVE

DESCRIPTION

I/O NOTES

C13

E12

G10

B12

B11

D11

B13

B14

C12

A14

B12

A12

D26

D27

D28

D29

D30

D31

Data Bus

LOW

12 mA I/O

• Asynchronous Address Bus

• Asynchronous Memory Write Byte Enable 1

HIGH:

nWE1

M16

N14

M15

M16

A0/nWE1

A1/nWE2

HIGH

12 mA

• Asynchronous Address Bus

• Asynchronous Memory Write Byte Enable 2

HIGH:

nWE2

M13

K16

K15

K14

L15

K12

K13

K16

J13

A2/SA0

A3/SA1

A4/SA2

A5/SA3

A6/SA4

J16

J14

J11

A7/SA5

J16

A8/SA6

• Asynchronous Address Bus

• Synchronous Address Bus

LOW

12 mA

H15

H10

H12

G15

G10

G11

F16

A9/SA7

H16

H14

G16

G14

G13

F16

A10/SA8

A11/SA9

A12/SA10

A13/SA11

A14/SA12

A15/SA13

• Async Address Bus

• Sync Device Bank Address 0

F14

E16

F13

A16/SB0

A17/SB1

LOW

12 mA

• Async Address Bus

• Sync Device Bank Address 1

E13

F11

D15

C16

B16

A15

A13

E14

D15

C16

C15

C14

B15

E11

A18

A19

A20

A21

A22

A23

A24

Asynchronous Address Bus

LOW

12 mA

• Async Memory Address Bus

• Smart Card Interface I/O (Data)

A25/SCIO

LOW: A25

LOW: A26

LOW: A27

LOW

12 mA I/O

• Async Memory Address Bus

• Smart Card Interface Clock

A26/SCCLK

A27/SCRST

• Async Memory Address Bus

• Smart Card Interface Reset

12 mA

nOE

Async Memory Output Enable

HIGH

No Change

12 mA

8 mA

nWE0

nWE3

Async Memory Write Byte Enable 0

Async Memory Write Byte Enable 3

D10

• Async Memory Chip Select 6

• Sync Memory Clock Enable 1 or 2

B10

C10

CS6/SCKE1_2

CS7/SCKE0

LOW: CS6

LOW: CS7

No Change

12 mA

• Async Memory Chip Select 7

• Sync Memory Clock Enable 0

A10

12 mA

A10

C14

A11

B10

C13

SCKE3

SCLK

Sync Memory Clock Enable 3

Sync Memory Clock

LOW

HIGH

LOW

I/O

No Change

nSCS0

Sync Memory Chip Select 0

12 mA

Preliminary data sheet

Rev. 01 — 16 July 2007

1...4 5 678 9 10...65

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