Datasheet > L5150CS

L5150CS

更新时间： 2024-01-26 02:29:32

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
34页	664K
描述
5 V low dropout voltage regulator

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技术参数
数据手册

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L5150CS 技术参数

是否Rohs认证：	符合	生命周期：	Active
零件包装代码：	SOIC	包装说明：	SOP, SOP8,.25
针数：	8	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	4.89	Base Number Matches：	1

L5150CS 数据手册

Block diagram and pins description

L5150CJ / L5150CS

Table 2.

Pin name

Pins description

PowerSSO-12

pin #

SO-8

pin #

Function

Reset adjustable threshold. Connected to an

appropriate external voltage divider, it allows to

properly set the reset threshold down to 3.5 V.

Connect to GND if not needed.

R_{es_Adj}

Reset output. Internally connected to V_othrough a

20 KΩ pull up resistor. This pin is pulled low when

V_o< V_{o_th}. Keep open if not needed.

R_es

Reset delay. Connect an external capacitor between

V_crpin and ground to adjust the reset delay time.

Keep open if not needed.

V_cr

GND

Ground reference.

Not connected.

5, 11, 8, 9

5 V regulated output. Block to GND with a ceramic

capacitor (C_o≥ 220 nF for regulator stability).

V_o

Supply voltage, block directly to GND on the IC with a

capacitor.

V_S

Early warning input. This pin monitors the V_Svoltage

level through a resistor divider. Connect to V_Sif not

needed.

EW_i

EW_o

TAB

Early warning output. Internally connected to V_o

through 20 KΩ pull up resistor. This pin is pulled low

when EW_iis below bandgap reference voltage. Keep

open if not needed.

TAB is connected to the substrate of the chip: connect

toGND or leave open (see Figure 2 for PowerSSO-12

only).

6/34

Doc ID 15542 Rev. 15

1...3 4 567 8 9...34

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