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KS88C8224 PDF预览

KS88C8224

更新时间: 2024-01-14 08:41:51
品牌 Logo 应用领域
三星 - SAMSUNG 时钟微控制器光电二极管外围集成电路
页数 文件大小 规格书
300页 2745K
描述
Microcontroller, 8-Bit, MROM, CMOS, PDIP42, 0.600 INCH, SDIP-42

KS88C8224 技术参数

生命周期:Obsolete零件包装代码:DIP
包装说明:SDIP,针数:42
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.84具有ADC:YES
地址总线宽度:位大小:8
最大时钟频率:8 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:
JESD-30 代码:R-PDIP-T42长度:39.1 mm
I/O 线路数量:28端子数量:42
最高工作温度:85 °C最低工作温度:-20 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:SDIP封装形状:RECTANGULAR
封装形式:IN-LINE, SHRINK PITCH认证状态:Not Qualified
ROM可编程性:MROM座面最大高度:5.08 mm
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:OTHER
端子形式:THROUGH-HOLE端子节距:1.778 mm
端子位置:DUAL宽度:15.24 mm
uPs/uCs/外围集成电路类型:MICROCONTROLLERBase Number Matches:1

KS88C8224 数据手册

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KS88C8216/C8224/P8224/C8316/C8324/P8324 MICROCONTROLLERS  
PRODUCT OVERVIEW  
Table 1–1. KS88C8316/C8324 Pin Descriptions  
Pin Description Circuit  
Pin Name  
P0.0–P0.7  
P1.0–P1.1  
Pin  
Type  
Pin  
Numbers  
Share  
Pins  
Type  
I/O  
General I/O port (8-bit), configurable for  
digital input or push-pull output.  
3
11–12, 35,  
38–42  
I/O  
General I/O port (2-bit), configurable for  
digital input or n-channel open-drain output.  
P1.0–P1.1 can withstand up to 6-volt loads.  
Multiplexed for alternative use as external  
interrupt inputs INT0–INT1.  
General I/O port (4-bit), configurable for  
digital input or n-channel open-drain output.  
P1.2–P1.5 can withstand up to 6-volt loads.  
High current port (10mA).  
7
5
14–15  
INT0–INT1  
P1.2–P1.5  
P1.6–P1.7  
16–19  
General I/O port (2-bit), configurable for  
digital input or push-pull output.  
3
2
20, 8  
2–7  
P2.0–P2.4,  
P2.6  
I/O  
General I/O port (6-bit). I/O mode or n-  
channel open-drain, push-pull output mode  
is software configurable. Pins can withstand  
up to 5-volt loads.  
P2.2: OTP serial clock pin  
P2.3: OTP serial data pin  
P2.5, P2.7  
P3.0–P3.1  
General I/O port (2-bit). I/O mode or n-  
channel open-drain, push-pull output mode  
is software configurable. Pins can withstand  
up to 5-volt loads.  
Each pin has an alternative function.  
P2.5: PWM0 (14-bit PWM output)  
P2.7: OSDHT (Halftone signal output)  
2
6
1, 21  
9–10  
PWM0  
OSDHT  
I/O  
General I/O port (2 bits), configurable for  
digital input or n-channel open-drain output.  
P3.0–P3.1 can withstand up to 5-volt loads.  
Multiplexed for alternative use as external  
interrupt inputs ADC0–ADC1.  
ADC0  
ADC1  
PWM0  
O
I
I
Output pin for 14-bit PWM0 circuit  
Analog inputs for 4-bit A/D converter  
External interrupt input pins  
2
6
7
2
1
P2.5  
P3.0–P3.1  
P1.0–P1.1  
P2.7  
ADC0–ADC1  
INT0–INT1  
OSDHT  
9,10  
14,15  
21  
Halftone control signal output for OSD  
O
Vblue, Vgreen  
Vred, Vblank  
H-sync  
O
Digital blue, green, red, and video blank  
signal outputs for OSD  
H-sync input for OSD  
V-sync input for OSD  
L-C oscillator pins for OSD clock frequency  
generation  
4
8
22–25  
I
26  
27  
28,29  
V-sync  
OSC  
,
I, O  
IN  
OSC  
OUT  
TEST  
I
13  
0V: Normal Operation Mode,  
Vdd: Test Mode and OTP Write Mode  
System clock pins  
System reset input pin, Factory test mode is  
activated when 12V is applied  
Power supply pins  
XIN, XOUT  
RESET  
I, O  
I
1
31,32  
33  
VDD, VSS  
CAPA  
I
8
13  
26  
Input for capture A module  
1–7  

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