ISL71001SLHM Datasheet
2.2
Pin Descriptions
Pin
Number
Pin Name
Description
1
M/S
Master/Slave input for selecting the direction of the bidirectional SYNC pin. For SYNC = Output
(Master mode), connect this pin to DVDD. For SYNC = Input (Slave Mode), connect this pin to
DGND.
2, 3, 4, 11,
12, 13
DGND
The digital ground associated with the internal digital control circuitry. Connect these pins directly
to the ground plane.
5
PGOOD
Power-good output. This pin is an open-drain logic output that is pulled to DGND when the output
voltage is outside a ±11% typical regulation window. This pin can be pulled up to any voltage from
0V to 5.5V, independent of the supply voltage. A nominal 1kΩ to 10kΩ pull-up resistor is
recommended. Bypass this pin to DGND with a 10nF ceramic capacitor to mitigate SEE.
6
SS
The soft-start input. Connect a ceramic capacitor from this pin to AGND to set the soft-start output
ramp time in accordance with Equation 1:
t
= C
V I
REF SS
(EQ. 1)
SS
SS
where:
t
= Soft-start output ramp time
SS
C
= Soft-start capacitor
SS
V
= Reference voltage (0.6V typical)
REF
I
= Soft-start charging current (23µA typical)
SS
Soft-start time is adjustable from approximately 2ms to 200ms.
The range of the soft-start capacitor should be 82nF to 8.2µF, inclusive.
7, 16, 17,
23, 32, 33,
48, 49
NC
There is no internal connection on this pin
8, 9, 10
DVDD
Bias supply inputs to the internal digital control circuitry. Connect these pins together at the IC and
locally filter them to DGND using a 1Ω resistor and a 1µF ceramic capacitor. Locate both filter
components as close as possible to the IC.
14, 15
18
AGND
AVDD
REF
Analog ground associated with the internal analog control circuitry. Connect these pins directly to
the ground plane.
Bias supply input to the internal analog control circuitry. Locally filter this pin to AGND using a 1Ω
resistor and a 1µF ceramic capacitor. Locate both filter components as close as possible to the IC.
19
Internal reference voltage output. Bypass this pin to AGND with a 220nF ceramic capacitor
located as close as possible to the IC. The bypass capacitor is needed to mitigate SEE. No current
(sourcing or sinking) is available from this pin.
20
FB
Voltage feedback input to the internal error amplifier. Connect a resistor from FB to VOUT and
from FB to AGND to adjust the output voltage in accordance with Equation 2:
V
= V
1 + R R
REF T B
(EQ. 2)
OUT
where:
V
V
= Output voltage
OUT
REF
= Reference voltage (0.6V typical)
R = Top divider resistor (Must be 1kΩ)
T
R = Bottom divider resistor
B
The top divider resistor must be 1kΩ to mitigate SEE. Connect a 4.7nF ceramic capacitor across
RT to mitigate SEE and to improve stability margins.
21
EN
Enable input to the IC. This is a comparator type input with a rising threshold of 0.6V and
programmable hysteresis. Driving this pin above 0.6V enables the IC. Bypass this pin to AGND
with a 10nF ceramic capacitor to mitigate SEE.
R34DS0014EU0101 Rev.1.1
Aug 10, 2021
Page 6
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